PCI Express 4.0 Lane Margining and its Advantages

By: Rita Horner, Senior Technical Marketing Manager, Synopsys

Designers face new challenges as they address the demand for higher bandwidth combined with faster time-to-market. While higher data rates enable higher bandwidth, they limit transmission distances (due to an increase in channel loss), degrade signal integrity and lower manufacturing yield. Addressing these challenges requires time and resources that can negatively influence system design schedules, or worse, may not be evident while the system is being designed.

PCI-SIG is addressing this challenge with the introduction of the PCI Express 4.0 (PCIe 4.0) lane margining at the receiver feature, allowing system designers to assess the performance variation tolerance of their system. Lane margining allows system designers to use PCIe 4.0 devices to measure the available electrical margin in each system. This article describes the lane margining feature and how it enables designers to deliver a more robust system on time.
 

Performance Variations within a System

PCI Express, a point-to-point interconnect, supports both internal and external connectivity either across a cable assembly or at the board level. Three common board level interconnect cases are chip-to-chip (with no connectors), an expansion card interface with a board and a connector and a backplane with multiple boards and connectors. In a complex backplane, there are many reasons that the signal integrity may degrade, including cross-talk, reflection, discontinuities, and channel loss. Figure 1 shows an example of channel loss differences across a FR-4 printed circuit board (PCB), where a 24-inch trace has much higher loss at 16 GT/s PCIe 4.0 than at 8 GT/s PCIe 3.0.

Environmental variances such as humidity and temperature also affect signal performance in a system, with changing PCB and connector characteristics affecting actual channel loss and signal integrity.

Influence of manufacturing and environmental variations are magnified at higher data rates. Designers must therefore carefully evaluate a high-speed system design for performance margins before it is released, avoiding last minute system optimizations which could cause a delay in time-to-market. Modeling and simulating all variations prior to building the final system can be extremely complex, time-consuming, and costly. To avoid these issues, system designers need access to an efficient and cost-effective method of conducting margin analysis.

Overcoming Performance Variations with Lane Margining

Lane margining at the receiver is a mandatory feature for all PCIe 4.0 ports, where the PCIe controller obtains margin information from the PHY receiver, while operating in active mode (L0 link state) at 16GT/s data rate, without the need for any additional external hardware. Using the lane margin control and error reporting features, the controller determines the margin in each PCIe lane of the system by evaluating the receiver eye width (time) and the eye height (signal amplitude – voltage). This allows for an efficient evaluation of the system’s margin at the PCIe device without the need for any additional setup.

The actual implementation of the margining feature in both the PHY and the controller is design-specific. Some designs utilize data or error samples in the PHY to evaluate the reporting of the signal eye information, and others may choose to simply stress the eye by injecting an appropriate amount of jitter into the data. The margin evaluation from the data provided by the PHY may also be processed differently by the controller. Controllers may use different offsets, voltage and timing steps for different levels of data collection granularities. In addition, different bit error tolerances may be set before exiting the margin evaluation.

As an example in figure 3, lane margining can be implemented by moving the data or error sample location in the PHY for error scanning. Starting from a sample location of the receiver eye, in incremental steps, the eye width may be scanned to the right and to the left to check for the minimum eye width margin. Optionally, the eye height can be scanned from the sample location to the top and bottom, for minimum eye height margin. The controller, using the margin information from the PHY, identifies where the failure occurs in the system and determines the lane margin. Figure 3 shows an example of a receiver eye at 16GT/s PCIe 4.0 in an optimal position with ample signal margins beyond the minimum eye width and eye height.

Summary

Performance variation and signal integrity degradation become greater as data rates double from PCIe 3.0s 8GT/s to PCIe 4.0s 16GT/s data rates. In addition, PCB manufacturing and environmental variances can cause increase in channel loss, cross talk, and channel discontinuities which result in increased system noise, deteriorated jitter performance and signal eye closure. The lane margining feature available in the upcoming PCI Express 4.0 specification will help system designers assess their design’s performance variation tolerance early in the design and production cycle by obtaining margin information with a PCIe 4.0 PHY and controller solution. This allows system designers to deliver a more robust system and better meet their time-to-market goals.

Synopsys PHY and Controller IP solutions for PCI Express 4.0 technology support the specification with lane margining. See the Synopsys PCIe 4.0 IP with lane margining video, demonstrated at PCI-SIG Santa Clara 2016.