Korea Workshops

VCS-Verdi Basic

Overview

In this course, you will be introduced to the industry's fastest engine VCS and the unified debug platform Verdi.  You will learn how to prepare the simulation with testbench and design, to use the general switches for simulation control and to utilize Verdi's basic features to analyze the problems brought up during the simulation.

Objectives

At the end of this workshop you should be able to:

• Compile the design and the testbench for the simulation.
• Prepare the debug database
• Dump the design contents for debug using Verdi
• use Verdi Fundamental skills such as nTrace, nSchema, nWave, nState and TFV, etc.

Audience Profile

Design or Verification engineers who are familiar with Hardware Description Language, Schematic, Waveform and State Diagram

Prerequisites

To benefit the most from the material presented in this workshop, you should have:

• A basic understanding of Verilog and/or VHDL
• A basic understanding of Schematic Diagram, Waveform and State Diagram
• Familiarity with UNIX workstations running X-windows
• Familiarity with vi, emacs, or other UNIX text editors

Course Outline – 1 Day

• Introduction to Verdi Technology
• VCS basic flow
• Setting for Waveform Dump
• nTrace / Design Management
• nSchema / Schematic View
• nWave / Waveform View
• nState / State Flow Chart Diagram
• Temporal flow View

SNPS Tools Used

• VCS vP-2019.06 or vO-2018.09
• Verdi  vP-2019.06 or vO-2018.09

 

Verdi Advanced

Overview

In this course, you will go through the extended utilization of the unified debug platform Verdi.  You will learn how to compare the waveforms from the simulations with the different scenario and be introduced to the diversity of debug application with Verdi.

Objectives

At the end of this workshop you should be able to:

• Compare the waveform against the reference.
• Plan the unified debug environment in regard to SystemVerilog, Coverage, etc.

Audience Profile

Design or Verification engineers who has the basic debug experience based on the waveform and the various testbench environment

Prerequisites

To benefit the most from the material presented in this workshop, you should have:

• A basic understanding of Verilog and/or VHDL
• A minimal experience of SystemVerilog, coverage, transaction, etc.
• Familiarity with UNIX workstations running X-windows
• Familiarity with vi, emacs, or other UNIX text editors

Course Outline – 1 day

• nCompare / FSDB comparison
• various debug utilization

SNPS Tools Used

• VCS vP-2019.06 or vO-2018.09
• Verdi vP-2019.06 or vO-2018.09

 

System Verilog Testbench

Overview

In this intensive, three-day workshop, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS. At the end of this workshop, you should have the skills required to write an object-oriented SystemVerilog testbench to verify a device under test with coverage-driven constrained-random stimulus using VCS.

You will learn how to develop an interface between the SystemVerilog test program and the Device Under Test (DUT). The workshop will explain how the intuitive object-oriented technology in SystemVerilog testbench can simplify verification problems. Randomization of data is covered to show how different scenarios for testing may be created. This workshop concludes with an in-depth discussion of functional coverage including a uniform, measurable definition of functionality and the SystemVerilog constructs that allow you to assess the percentage of functionality covered, both dynamically and through the use of generated reports.

A lab on packages and methodology will introduce you to the basic concepts used in methodologies such as UVM and VMM. To reinforce the lecture, and accelerate mastery of the material, you will complete a challenging test suite for a real-world system-based design.

This workshop does not cover basic Verilog or VHDL concepts like modules/entities, initial and always blocks, processes etc.

Objectives

At the end of this workshop you should be able to:

• Build a SystemVerilog verification environment
• Define testbench components using object-oriented programing
• Develop a stimulus generator to create constrained random test stimulus
• Develop device driver routines to drive DUT input with stimulus from generator
• Develop device monitor routines to sample DUT output
• Develop self-check routines to verify correctness of DUT output
• Abstract DUT stimulus as data objects
• Execute device drivers, monitors and self-checking routines concurrently
• Communicate among concurrent routines using events, semaphores and mailboxes
• Develop functional coverage to measure completeness of test
• Use SystemVerilog Packages

Audience Profile

Design or Verification engineers who write SystemVerilog testbenches at the block or chip level.

Prerequisites

To benefit the most from the material presented in this workshop, you should have:

• A basic understanding of digital IC design
• Familiarity with UNIX workstations running X-windows
• Familiarity with vi, emacs, or other UNIX text editors
• A basic understanding of Verilog and/or VHDL and their use in simulations

Course Outline – 2 days

Day 1

• The Device Under Test
• SystemVerilog Verification Environment
• SystemVerilog Testbench Language Basics - 1
• SystemVerilog Testbench Language Basics - 2
• Managing Concurrency in SystemVerilog

Day 2

• Object Oriented Programming: Encapsulation
• Object Oriented Programming: Randomization
• Object Oriented Programming: Inheritance
• Inter-Thread Communications
• Functional Coverage
• SystemVerilog UVM preview

SNPS Tools Used

• VCS 2019.06
• Verdi 2019.06

 

UVM

Overview

In this hands-on workshop, you will learn how to develop a UVM SystemVerilog testbench environment which enables efficient testcase development. Within the UVM environment, you will develop stimulus sequencer, driver, monitor, scoreboard and functional coverage. Once the UVM environment has been created, you will learn how to easily manage and modify the environment for individual testcases. You will learn how to use the configuration database to control both, component behavior and stimulus generation. You will use the power of Object-oriented programming to easily replace component and transaction objects with their derived-class variations. You will learn how to use callbacks to increase the controlability and observability of the testbench. You will also learn how to model registers in UVM that simplity the configuring and testing the registers in your device.

Objectives

At the end of this workshop the student should be able to:

• Develop UVM tests
• Implement and manage report messages for printing to terminal or file
• Create random stimulus and sequences
• Build and manage stimulus sequencers, drivers and monitors
• Create configurable agents containing sequencer, driver and monitor for re-use
• Create and manage configurable environments including agents, scoreboards, TLM ports and functional coverage objects
• Implement a collection of testcases each targeting a corner case of interest
• Create an abstraction of DUT registers and manage these registers during test, including functional coverage and self-test

Audience Profile

Design or Verification engineers who develop SystemVerilog testbenches using UVM base classes.

Prerequisites

To benefit the most from the material presented in this workshop, students should have completed the SystemVerilog Testbench workshop.

Course Outline – 3 days

Day 1

• SystemVerilog OOP Inheritance Review
• UVM Structural Overview
• Modeling Stimulus (UVM Transactions)
• Creating Stimulus Sequences (UVM Sequence)

Day 2

• Component Configuration and Factory
• TLM Communications
• Scoreboard & Coverage
• UVM Callback

Day 3

• Advance Sequence/Sequencer
• Phasing and Objections◦Managing Objections within Component Phases
• Register Layer Abstraction (RAL)
• Summary

SNPS Tools Used

• VCS 2019.06
• Verdi 2019.06

 

Verdi Advanced

Overview

VC LP is a multi-voltage, static low power rule checker that allows engineers to rapidly verify designs that use voltage control based techniques for power management.

Objectives

After completing this lab, you should be able to:

• Read Designs in Verification compiler Static Low Power (VC LP)
• Load power intent file in VC LP
• Perform checks on UPF and Netlist with power and ground connected
• Generate reports to investigate violations
• Identify issues relating to PST merging
• Debug static LP issues at the UPF, post-synthesis and post-place and route stages of design process
• Using the GUI to debug
• Using shell to debug

Audience Profile

Design or Verification engineers who need to verify UPF at RTL and Gate Netlist level

Prerequisites

• HDL language (verilog,vhdl,system-verilog)
• UPF Experience
• Overall of Design Implementation & Verification Flow

Course Outline – 1 day

• Low Power Flow & VC LP Overview
• Setting Up VC LP & Running Checks
• Reviewing Reports
• Tcl Query & Debug
• Low Power GUI
• VC LP New Features

SNPS Tools Used

• VERDI 2019.06
• VCSTATIC 2019.06

 

Spyglass-Power

Overview

The SpyGlass Power Estimation and Exploration solutions are very closely linked and calibrated to give excellent power correlation with gate-level and silicon estimates when setup correctly. This is a must-have for you to proceed confidently into power reduction on your design.

Objectives

At the end of this workshop you should be able to:

• Familiraize with the user with spyglass-power setup and auidt it before any power related runs
• How to identify regions of interesting simulation activity and estimate the power of Gate level design
• How to generate calibration data for accurate RTL power estimation, and verify the data generated is useful and correct
• Generate accurate RTL power estimation results using calibration data and correlate these results with gate level power numbers
• Identify power hungry hierarchies/registers/operators in the deisgn by doing Power Exploration on the RTL design using various metrics/tool views

Audience Profile

• RTL Designer
• FrontEnd Engineer
• SpyGlass User(option)

Prerequisites

• HDL language (verilog,vhdl,system-verilog)
• Overall of Design Implementation & Verification Flow

Course Outline – 1 day

• SpyGlass Power Overview
• SpyGlass RTL Power Estimation
• Power Estimation Setup
• Power Estimation Advanced Topics
• SpyGlass Power Exploration
• Metrics Driven Power Exploration

SNPS Tools Used

• SpyGlass Power Estimation 2019.06

 

Spyglass-CDC

Overview

SpyGlass® CDC solution is used to detect issues related with Clock Domain Crossings (CDC) in a design. It ensures that proper synchronization is added in the circuit to avoid such issues.

Objectives

At the end of this workshop you should be able to:

• Clock domain crossing [CDC] issues, traditional solutions, and need for a new solution
• Types of CDC problems
• Requirements to run SpyGlass-CDC
• How SpyGlass to identify clock domain crossings that cause metastability in the design
• The spreadsheet viewer in sorting CDC violations
• How SpyGlass to identify badly synchronized resets

Audience Profile

• RTL Designer
• FrontEnd Engineer
• SpyGlass User(option)

Prerequisites

• HDL language (verilog,vhdl,system-verilog)
• Overall of Design Implementation & Verification Flow

Course Outline – 1 day

• CDC Setup
• CDC Setup Check
• CDC Structural Verification
• Qualifier based synchronization verification and enforceable constraints
• Glitch categorization and verification
• Coherency/Convergence categorization and verification
• Hierarchical Verification Flow

SNPS Tools Used

• SpyGlass CDC 2019.06

 

DC(G)

Overview

This course covers the RTL synthesis flow: Using Design Compiler in Topographical mode to synthesize a block-level RTL design to generate a gate-level netlist with acceptable post-placement timing and congestion. You will learn how to: Read in hierarchical block-level RTL designs; Load libraries, technology data and floorplan constraints; Apply and verify constraints for complex design timing; Use timing- and congestion-focused DC Ultra and DC Graphical optimization features, which includes the SPG flow, to achieve post-placement timing closure and acceptable congestion; Analyze synthesis results for timing and congestion; Generate output data required by physical design or layout tools.

The course includes labs to reinforce and practice key topics discussed in lecture. Optionally, you will verify the logic equivalence of synthesis transformations (such as datapath optimizations and register retiming) to that of an RTL design using Formality.

All the covered commands and flows are printed separately on an 8-page “Job Aid” hand-out, which the student can refer to back at work

Objectives

At the end of this workshop the student should be able to:

• Load the logic libraries, as well as physical technology and design data which are required for synthesis in DC Topographical mode
• Read in hierarchical RTL designs
• Constrain a complex design for timing (includes: ideal clock modeling using master, virtual and generated clocks; input and output port constraints; modeling mutually-exclusive, asynchronous and multi-cycle clocks)
• Apply DC Ultra techniques to achieve timing closure with good post-layout correlation (includes: auto-ungrouping, boundary optimization, test-ready synthesis, adaptive and register retiming, prioritizing and enabling high-effort timing optimization, path groups, TNS-driven placement)
• Take advantage of DC-Graphical features to improve timing closure, reduce congestion, and improve post-placement timing correlation (includes: register duplication, net layer optimization, netlist topology optimization and physical guidance to ICC or ICC II)
• Generate and interpret timing and constraint reports
• Analyze global route-based congestion
• Generate output data (netlist, constraints, scan-def, coarse placement) that is needed to implement the layout (place and route)
• Write DC-Tcl scripts to constrain designs, and run synthesis

Audience Profile

ASIC digital designers who need to use Design Compiler to synthesize RTL designs to gates.

Prerequisites

Prior experience with Design Compiler is not needed. An understanding of basic digital ASIC design concepts is assumed, including combinational and sequential logic functionality, and setup and hold timing. The ability to work in a Unix/X-windows environment, using a text editor such as emacs, vi, pine, is required for labs.

Course Outline – 3 days

Day 1

• Introduction to Synthesis
• Data Setup for DC Topographical Mode
• Accessing Design and Library Objects
• Constraints: Reg-to-Reg and I/O Timing

Day 2

• Constraints: Reg-to-Reg and I/O Timing
• Constraints: Input Transition and Output Loading
• DC Ultra Synthesis Techniques

Day 3

• Timing Analysis
• Constraints: Multiple Clocks and Exceptions
• DC Graphical: SPG Flow, Congestion, Layout GUI
• Constraints: Complex Design Considerations
• Post-Synthesis Output Data
• Conclusion

SNPS Tools Used

• Design Compiler 2017.09-SP4
• Formality 2017.09-SP4

 

Formality

Overview

At the end of this one day, trainee will understand the basic usage of running formality based on the concept of equivalence check

For concept of understanding abort and inconclusive and how to resolve the issued point from Design Compiler optimization

For debugging usage to analyze and identify root-cause using real failure in Tape-out design

To starch goals, trainee will be advised working model of pattern analysis, error pattern edit and its modification

For SOC design, introduced top-level flat formality flow and hierarchical approach as well as usage of UPF format

Objectives

At the end of this lecture, the trainee should be able to:

• How to use error pattern viewer and schematic viewer w. understanding its meaning.
• Perform extended work-model to resolve hard verification cf. abort and inconclusive
• Able to perform basic debugging procedure of using various cases
• Able to guide DC-synthesis part to avoid failures and Designware related issue.
• Perform to Equivalent check using UPF mode by controlling power isolation strategies

Audience Profile

ASIC digital designers w. RTL design knowledge and Design Compiler experience.

Required to experience of designware and optimization in their designs during RTL synthesis and mode configuration.

Prerequisites

Experience in elaboration and synthesizing RTL to gate level design

Course Outline – 1 day

• Using Formality
•     Flow Overview
•     Guidance
•     Read
•     Setup
•     Match
•     Verify
•     Debug
• Debugging Failing verification Flow
• Frequently Used Debugging Tools
• Common Problems
• Debugging Inconclusive verifications
• Documentation and Help

SNPS Tools Used

• Formality, Design Compiler

 

Lower power Flow

Overview

At the end of this one day, seminar based, workshop you will understand how to apply both traditional and UPF based power optimization techniques during RTL synthesis and scan insertion:

For single voltage designs, you will learn how to apply the 2 traditional power optimization techniques of clock gating and leakage power recovery, optimizing for dynamic power and leakage power respectively.

For multi-voltage or multi-supply designs, you will learn how to apply the IEEE 1801 UPF flow that uses a power intent specification which is applied to RTL designs. You will understand how to synthesize RTL designs for the required power intent and power-optimization requirements using top-down vs. hierarchical UPF methodologies. You will also learn how to insert scan chains to the synthesized netlist ensure that the gate level design does not have any multi-voltage violations, before writing out design data for Place and Route.

Objectives

At the end of this workshop the student should be able to:

• Apply clock gating to a design at the RTL and gate level
• Perform multi-stage, hierarchical, and power driven clock gating
• Perform leakage optimization using multi Vt libraries
• Restrict the usage of leaky cells
• Specify power intent using UPF
• Demonstrate flexible isolation strategy in UPF 2.0
• Check for UPF readiness of library, reporting PG pins
• State the purpose of SCMR attribute in library
• Recognize tradeoff when using dual vs. single rail special cells
• Correctly specify PVT requirements
• State how the 6 special cells are synthesized
• Describe supply net aware Always on Synthesis
• Apply 2 key debugging commands in a UPF flow
• Control voltage, power domain mixing when inserting scan chains
• Allow/prevent the reuse of level shifters and isolation cells between scan and functional paths
• Minimize toggle in functional logic during scan shifting
• Validate SCANDEF information for place and route

Audience Profile

ASIC digital designers, with Design Compiler experience, having need to minimize power consumption in their designs during RTL synthesis and scan insertion.

Prerequisites

Experience in synthesizing RTL to gate level design using DC Topographical/Graphical, or have attended the Design Compiler 1 workshop.

Course Outline – 1 day

Day 1

• Clock Gating
• Leakage Power Optimization
• Power Intent using IEEE 1801 UPF
• Library Requirements
• Synthesis with UPF
• Power Aware DFT

SNPS Tools Used

The lecture material of this workshop is based on the following Synopsys tools:

• Design Compiler Topographical 2013.03
• Power Compiler 2013.03
• DFT Compiler 2013.03

 

Spyglass-DFT

Overview

In this workshop, you will learn to use TestMAX Advisor (previously known as SpyGlass DFT) to perform RTL testability analysis that will allow you to fine-tune your RTL early in the design cycle. This will verify the design scan readiness and Test Robustness and work towards meeting fault and test coverage goals. The workshop introduces basic DFT principles and explores essential techniques to setup runs. It will explain the various audit reports and how to use them when analyzing the design. It will also show how to use the GUI for debug of violations and explain various annotations seen on schematics. It will also cover running transition At-speed coverage audit as well as random resistant fault analysis. To complete the flow, it will also cover how to run connectivity check feature.

Objectives

At the end of this workshop you should be able to:

• Setup a project file and SGDC file to run a basic testability check
• Run the goal and analyze the results using GUI and reports
• Recognize common design constructs that cause typical DFT violations
• Suggest techniques to correct certain DFT violations
• Run transition delay coverage audit
• Explore your design for Random Resistant Faults and learn how to add test points
• Explore different test points that could be added to improve testability and links to Physically aware DFTMAX flow
• Use TestMAX Advisor to verify scan chains in a scan inserted netlist
• Learn how to write a script to check on connectivity requirements of your design to verify integration of netlist at top level
• Learn how TestMAX Advisor is called from the TestMAX Manager flow

Audience Profile

Design and Test engineers who need to identify and fix DFT violations in their RTL to ensure a successful scan insertion into multi-million gate SoCs, and ensure high test coverage results in ATPG.

Prerequisites

There are no prerequisites for this workshop. Prior experience with Design Compiler, other SpyGlass products and writing Synopsys Tcl scripts is useful, but not required.

Course Outline – 1 day

• Introduction
• TestMAX Advisor Flow
• Early Testability Goals and Reports
• Debug using the GUI
• Transition Delay Checks
• Random Resistant Fault Analysis and Test Points
• Post stitch DRC Checks
• Connectivity Checks
• Flow With TestMAX Manager
• Conclusion

SNPS Tools Used

• TestMAX Advisor / SpyGlass DFT 2019.06

 

 

TestMAX DFT

Overview

In this workshop you will learn to use TestMAX DFT to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and to insert scan using top-down and bottom-up flows. The workshop explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length and reusing functional pins for scan testing, inserting an On-Chip Clocking (OCC) controller for At-Speed testing using internal clocks; and using DFTMAX scan compression and DFTMAX Ultra to insert additional DFT hardware to reduce the test time and the test data volume required for a given fault coverage.

Objectives

At the end of this workshop you should be able to:

• Create a test protocol for a design and customize the initialization sequence, if needed, to prepare for DFT DRC checks
• Perform DFT DRC checks at the RTL, pre-DFT, and post-DFT stages
• Recognize common design constructs that cause typical DFT violations
• Automatically correct certain DFT violations at the gate level using AutoFix
• Implement top-down scan insertion flow achieving well-balanced scan chains
• Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and Place & Route
• Develop a bottom-up scan insertion script for full gate-level designs to use Test Models at the top-level to improve capacity and runtime
• Insert an On-Chip Clocking (OCC) controller to use for At-Speed testing with internal clocks
• Modify a scan insertion script to include DFTMAX and/or DFTMAX Ultra compression
• Insert a core wrapper

Audience Profile

Design and Test engineers who need to identify and fix DFT violations in their RTL or gate-level designs, insert scan into multi-million gate SoCs, and export design files to ATPG and P&R tools.

Prerequisites

There are no prerequisites for this workshop. Prior experience with Design Compiler, Design Vision and writing Synopsys Tcl scripts is useful, but not required.

Course Outline – 3 days

Day 1

• Introduction
• Scan Testing and Flows
• Test Protocol
• DFT Design Rule Checks
• DFT DRC GUI Debug

Day 2

• DRC Fixing
• Top-Down Scan Insertion
• Advanced Scan Insertion
• Export

Day 3

• Bottom-Up Scan Insertion
• On-Chip Clocking (OCC)
• DFTMAX
• Advanced Topics
• Conclusion

SNPS Tools Used

• TestMAX DFT 2019.03-SP3
• Design Vision 2019.03-SP3
• Design Compiler 2019.03-SP3
• TestMAX ATPG 2019.03-SP3

 

TestMAX+DSM

Overview

In this three-day workshop, you will learn how use TetraMAX®--Synopsys' ATPG Tool--to perform the following tasks:

• Generate test patterns for stuck-at faults given a scan gate-level design created by DFT Compiler or other tools
• Describe the test protocol and test pattern timing using STIL
• Debug DRC and stuck-at fault coverage problems using the Graphical Schematic Viewer
• Troubleshoot fault coverage problems
• Save and validate test patterns
• Troubleshoot simulation failures
• Diagnose failures on the ATE

This workshop also includes an overview of the fundamentals of manufacturing test, such as:

• What is manufacturing test?
• Why perform manufacturing test?
• What is a stuck-at fault?
• What is a scan chain?

This workshop also includes an overview of the DFTMAX and Power-Aware APTG features in TetraMAX®.

Objectives

At the end of this workshop the student should be able to:

• Incorporate TetraMAX® ATPG in a design and test methodology that produces desired fault coverage, ATPG vector count and ATPG run-time for a full-scan or almost full-scan design
• Create a STIL Test Protocol File for a design by using Quick STIL menus or commands, DFT Compiler, or from scratch
• Use the Graphical Schematic Viewer to analyze and debug warning messages from Design Rule Check or fault coverage problems after ATPG
• Describe when and how to use at least three options to increase test coverage and/or decrease the number of required test patterns
• Save test patterns in a proper format for simulation and transfer to an ATE
• Validate test patterns in simulation using MAX Testbench
• Describe the difference between the Transition Delay and Path Delay fault models
• Use timing exceptions with At-Speed testing to mask slow cells
• Limit switching activity with Power-Aware ATPG
• Perform Transition Delay testing including Slack-Based Transition Delay
• Use On-Chip Clocking (OCC) to provide launch and capture clock pulse for At-Speed testing
• Generate critical paths from PrimeTime for performing Path Delay testing
• Use TetraMAX® diagnosis features to analyze failures on the ATE

Audience Profile

ASIC, ASIC, SoC or Test Engineers who perform ATPG at the Chip or SoC level.

Prerequisites

Prerequisites for the workshop include:

• Understanding of digital IC logic design
• Working knowledge of Verilog or VHDL language
• Familiarity with UNIX workstations running X-windows
• Familiarity with vi, emacs, or other UNIX text editors

To benefit the most from the material presented in this workshop, students should have taken the DFT Compiler workshop or possess equivalent knowledge of DFT Compiler, scan insertion, and the fundamentals of manufacturing test.

Course Outline – 3 days

Day 1

• Introduction to ATPG Test
• Building ATPG Models
• Running DRC
• Controlling ATPG

Day 2

• Minimizing ATPG Patterns
• Pattern Validation
• Introduction to At-Speed Testing
• At-Speed Constraints

Day 3

• Transition Delay Testing
• On-Chip Clocking Support
• Path Delay Testing
• Diagnosis
• Conclusion

SNPS Tools Used

• TetraMAX 2017.09-SP3
• VCS 2017.12-SP1
• PrimeTime 2017.12-SP1
• Verdi 2017.12-SP1

 

PrimeTime

Overview

In this workshop you will learn to perform Static Timing Analysis (STA) and Signal Integrity (SI) analysis using the PrimeTime Suite of tools.  The workshop will teach our recommended methodologies for a) identifying constraints that are either incomplete/incorrect causing invalid timing violations or hiding real timing violations, and b) generating reports by executing the appropriate high-level summary reports to initiate your analysis, customizing and interpreting detailed timing reports for debugging.

You will exercise several timing checks on the design as well as analyze designs with complex timing requirements. The workshop will address a number of signoff / timing closure topics including Path Based Analysis (PBA), CCS Time and Noise Libraries, Parametric On Chip Variation (POCV), Advanced Waveform Propagation (AWP), ECO What-if analysis, Distributed Multi Scenario Analysis (DMSA) and Hyperscale Analysis.

The workshop includes comprehensive hands-on labs, which provide an opportunity to apply several key concepts covered during the lectures.

Objectives

At the end of this workshop the student should be able to:

• List the sequence of steps needed for Static Timing Analysis flow in PrimeTime
• Create and/or restore a saved session
• Identify opportunities to improve STA run time
• Verify design constraints, look for untested timing checks and address the issues using a Job Aid
• Systematically generate and interpret reports for summary and detailed design/timing information
• Constrain/Identify design clocks that are synchronous, asynchronous and are mutually exclusive
• Find which clocks are interacting and validate correct clock interactions
• Exercise Setup/Hold, Recovery/Removal, Clock Gating setup/hold, Data to Data setup/hold and Minimum pulse width checks generating reports accordingly
• Analyze timing situations involving Latches, Multi cycle paths, Combinational feedback loops, and Non unate cells along clock paths
• Debug Timing Reports when the findings are incorrect/questionable
• Account for statistical on-chip delay variations using Parametric OCV (POCV) analysis
• Enable Advanced Waveform Propagation (AWP) to address waveform distortions and to improve timing correlation with SPICE
• Determine when and how to use path-based analysis (PBA) to achieve timing accuracy
• Perform crosstalk delay analysis in PrimeTime-SI using key reports from the shell and the GUI
• Generate crosstalk noise analysis reports discussing the benefits to using CCS Noise libraries
• Using (Physically Aware) ECO steps, to fix Timing, DRC and Noise violations and to reduce power
• Address handling of a large number of scenarios and very large designs using respectively the techniques of Distributed Multi Scenario Analysis (DMSA) and Hyperscale Analysis

Audience Profile

ASIC digital designers, or verification engineers, who will be using PrimeTime to perform Static Timing Analysis (STA) and Signal Integrity (SI) analysis on pre- or post-layout gate level designs, and who need to validate STA constraints for correctness and completeness.

Prerequisites

To benefit the most from the material presented in this workshop, students should:

• Have a basic understanding of digital IC design
• Understand elements of gate level design: chip vs. block level, sequential vs. combinational logic, clock tree vs. data path, pre- vs. post- layout differences
• Have familiarity with UNIX and a UNIX text editor of your choice

No prior PrimeTime knowledge or experience is needed to attend this workshop

Course Outline – 3 days

Day 1: STA Flow and Recommended Methodology

• STA Concepts and Flow in PrimeTime
• Methodology: Qualifying Constraints
• Methodology: Generating Reports

Day 2: Best Practices

• Constraining Multiple Clocks
• Additional Checks and Constraints
• Correlation:  POCV and AWP Analysis
• Signoff: Path Based Analysis (PBA)

Day 3: Signoff Considerations (Continued)

• Signal Integrity: Crosstalk Delay Analysis
• Signal Integrity: Crosstalk Noise Analysis
• Timing Closure: ECO/What If Analysis
• Large Data: DMSA and Hyperscale Analysis
• Conclusion

SNPS Tools Used

• PrimeTime 2019.03-SP3
• PrimeTime-SI 2019.03-SP3
• PrimeTime-ADV 2019.03-SP3
• PrimeTime-ADV-PLUS 2019.03-SP3 (Optional)
• PrimePower 2019.03-SP3 (Optional)

 

PrimePower

Overview

In this course, you will study PrimePower's signoff power analysis capability to accurately analyze peak power, average power, clock network power, and multi-voltage power.

Skills learned include:

• Determining possible analysis methods, based on the available data and the application needs
• Applying a methodology to confirm that the power analysis performed was complete and correct
• Applying debugging technique(s) if necessary
• Generating and interpreting all of the standard PrimePower reports for switching activity peak power, average power, clock network power, and multi-voltage power analysis
• Generating and viewing peak-power waveforms

To analyze power on multi-voltage designs, you will be using the unified power format (IEEE 1801 UPF) based flow.

Objectives

At the end of this workshop the student should be able to:

• Read the required timing and power data; verify their completeness
• Perform peak and average power analysis in the GUI and shell interface
• Perform SDC clock-frequency-based power scaling in VCD/SAIF average power flow
• Generate VCD and SAIF switching activity files by simulating RTL and gate-level designs
• Distinguish between event-based and cycle-accurate peak power (CAPP) analysis
• Perform delay shifted peak power using RTL/ZD-GL FSDB/VCD
• Dump and view peak power waveforms
• Perform conditional peak power analysis
• Determine quality of analyses from switching activity and power reports
• Estimate pre-layout clock-tree power
• Annotate clock-network power
• Determine power savings due to clock gating
• Specify PVT corner and libraries for multi -voltage power analysis
• Interpret UPF power intent of a multi voltage design
• Perform UPF-flow-based multi-voltage power analysis
• Perform concurrent multi-rail power analysis using UPF

Audience Profile

Design or Verification engineers who need to choose an appropriate analysis technique and perform signoff power and mulit-voltage design analysis using PrimePower.

Prerequisites

To benefit the most from the material presented in this workshop, students should:

A. Have taken the PrimeTime workshop

OR

B. Possess equivalent knowledge with PrimeTime including:

• Restoring a previously-saved design
• Reading and linking a design
• Applying timing constraints
• Generating and interpreting timing reports using the report_timing command

Course Outline – 1 day

• Introduction to Power Analysis
• Average Power Analysis
• Peak Power Analysis
• Clock Network Power Analysis
• Multivoltage Power Analysis

SNPS Tools Used

• PrimePower 2018.06
• Verdi/nWave 2017.12-SP2
• VCS 2017.12-SP2

 

Fusion Compiler

Overview

Learn to use Fusion Compiler to perform complete physical synthesis, which is the unification of traditional synthesis and ICCII placement functionality. At the end of the workshop, you will have a design that can be passed on to clock tree synthesis and routing.

• Day 1 topics include GUI usage and extensive GUI exercises; Creating the design library and referencing standard cell and IP libraries, reading RTL and dealing with “dirty” or incomplete RTL; Understanding objects, blocks and application options; Details of the seven optimization stages of the compile_fusion flow and the absolute minimum setup required for physical synthesis.
• Day 2 covers loading UPF and dealing with incomplete or non-existing UPF; Loading floorplan data and using Fusion Compiler’s advanced auto-floorplanning features; Performing MCMM setup (modes, corners, scenarios), fixing timing setup issues, and accounting for on-chip variation; Configuring concurrent clock and data (CCD) optimization, dealing with macro skew requirements, enabling trial clock tree synthesis (CTS) and performing set up for CTS (non-default routing rules, clock cell selection, etc.)
• Day 3 covers how NDM cell libraries are constructed and what source data is required, and how to create a tech-only NDM library for ease of use; Power optimization which includes leakage, dynamic and total power optimization, multibit optimization, clock gate insertion, XOR self-gating and performing trial CTS-based ICG optimization; Various techniques to improve timing and congestion, DesignWare, and pre-route layer estimation technologies. Hierarchical synthesis using abstracts is described in detail.

Objectives

At the end of this workshop you should be able to use Fusion Compiler to:

• Navigate the Fusion Compiler layout view◦Control object and layer visibility
• Select and query layout objects
• Rearrange panels in the GUI
• Generate timing histograms
• Use RTL cross-probing
• Use help and man to get help and additional information about commands and options
• Create a design library
• Read the RTL
• Manage incomplete RTL
• Query objects and retrieve design information using attributes
• Query and set application options to control Fusion Compiler’s behavior

Describe the:

• Unified RTL-to-GDS synthesis and implementation flow
• Seven stages of compile_fusion
• Recommended test insertion flow
• •Perform minimum recommended setup steps prior to compile
• •Execute the unified physical synthesis flow
• •Apply the power intent (UPF)
• •Manage RTL-PG constructs
• •Enable Incomplete UPF support
• •Apply a floorplan
• •Configure Fusion Compiler to create a floorplan on-the-fly
• Perform MCMM setup:
•         Define the corners, modes and scenarios required for analysis and optimization
•         Load the MCMM constraints
•         Configure scenario setup
•         Model on-chip variation
• Handle infeasible timing paths
• Describe how CCD optimization can improve setup timing
• Apply CCD controls that limit where and how much useful skew is applied
• Enable useful skew for macro banks
• Enable trial CTS to improve CCD results
• Describe what elements an NDM cell library contains
• Describe the flows for cell library creation
• Create an NDM technology-only library for ease-of-use
• Control leakage, dynamic or total power optimization
• Use multibit banking
• Control ICG insertion for dynamic power reduction
• Invoke ICG optimization to address critical enable pin setup timing
• Handle spare cells
• Report and control data path architecture selection
• Recognize congestion issues and take measures
• Increase timing optimization effort
• Control cell density
• Describe the available layer aware techniques
• List the steps necessary for top-level implementation
• Describe what an abstract is and what it contains
• Describe how to assemble the top-level design

Audience Profile

Design engineers who will be using Fusion Compiler to perform Physical Synthesis.

Prerequisites

Prior working knowledge of Design Compiler Graphical is expected. Superficial knowledge of ICC II placement is helpful.

Course Outline – 3 days

Day 1

• Introduction and GUI use (Lecture + Lab)
• Reading RTL (Lecture + Lab)
• Objects, Blocks and App Options (Lecture only)
• Compile Flows and Minimum Setup (Lecture + Lab)

Day 2

• Loading UPF and Floorplan (Lecture only)
• Timing Setup (Lecture + Lab [4+5])
• CCD Optimization (Lecture + Lab)

Day 3

• NDM Cell Libraries (Lecture only)
• Power Optimization (Lecture + Lab)
• Additional Compile Settings and Techniques (Lecture only)
• Hierarchical Synthesis (Lecture only)
• Customer Support (Lecture only)

SNPS Tools Used

• Fusion Compiler 2019.03-SP2

 

ICC2-DP

Overview

In this hands-on workshop, you will use IC Compiler II to create chip and block-level floorplans using a hierarchical (top-down) design planning approach. The focus is on multi-voltage (UPF) system-on-a-chip (SoC) designs with multiple levels of physical hierarchy, which can contain a mix of multiply-instantiated blocks (MIBs), black boxes, and partial netlists.

• Day 1: gives you a quick overview of the DP flow, and then goes into the details of creating your initial flip-chip layout, and performing design exploration to decide on the chip's multi-level physical partitions. You then learn how to split chip level constraints and UPF. You will create block abstracts of the design and move on to automatic shaping of the blocks and voltage areas within the chip, as well as hierarchical macro and standard cell placement. This is in tandem with congestion and connectivity analysis.
• Day 2: covers Pattern-based Power Network Synthesis (PPNS) to design a complex multi-voltage chip-level power network, which is then built for each sub block in an automated and distributed fashion. Power switch insertion is also discussed. Next, the discussion moves to pin placement, including topological constraints and a detailed discussion on feedthroughs, then into topics on hierarchical timing estimation and timing budgets, which are used for block implementation. Top-level integration and implementation as well as budget shells are then also discussed and how they are used for top-level implementation. The day wraps up by explaining how to use black boxes throughout the design planning flow.

The lectures are accompanied by hands-on labs.

Objectives

At the end of this workshop you should be able to use IC Compiler II to:

• Create an NDM design library
• Read the Verilog outlines
• Initialize the chip-level floorplan
• Place the flip-chip bumps
• Place the Signal IO drivers/pads
• Explore the physical design hierarchy
• Commit the physical sub-blocks
• Split full design UPF and timing constraints
• Create placement block abstracts
• Shape and place blocks and voltage areas
• Place macros and standard cells
• Perform connectivity and congestion analysis
• Insert power pads and connect them to the bumps
• Build hierarchically distributed PG rings, meshes and connections for macros and standard cells using Pattern-based Power Network Synthesis
• Insert boundary, end-cap and tap cells
• Insert and connect power switches
• Verify and analyze the power mesh
• Perform pin placement including feedthroughs for all blocks
• Estimate the design's timing to determine feasibility of the design
• Create block budgets for implementation
• Create budget shells for top-level design implementation
• Use black boxes in the design planning flow

Audience Profile

ASIC, back-end, or layout designers who will be using IC Compiler II to perform design planning on multi-voltage SoC designs

Prerequisites

An understanding of fundamental floorplanning concepts is required. It is assumed that the requirements to create a good floorplan are known.

While prior working knowledge of IC Compiler II or IC Compiler would be very helpful, it is not required. The workshop, however, does assume a basic understanding of ICC II design/timing setup and configuration concepts (corners/modes/scenarios).

Course Outline – 2 days

Day 1

• Introduction (Lecture only)
• Initial Design Planning (Lecture + Lab)
• Shaping and Placement (Lecture + Lab)

Day 2

• Build the Power Network (Lecture + Lab)
• Pins, Timing and Budgets (Lecture + Lab)
• Using Black Boxes (Lecture only)

SNPS Tools Used

• IC Compiler II 2018.06-SP5

 

ICC2 General

Overview

Learn to use IC Compiler II to run a complete place and route flow on block-level designs. The flow covered within the workshop addresses the main design closure steps for multi-voltage designs, with multi-corner multi-mode (MCMM) timing and power challenges. All topics are accompanied by very engaging hands-on lab exercises.

• Day 1 topics include: ICC II GUI usage; objects, blocks and application options; block-level floorplanning; placement and incremental post-placement optimizations.
• Day 2 topics include: Library preparation for IC Compiler II NDM cell libraries; IC Compiler II's re-architected multi-corner/mode/scenario design setup process; classic clock tree synthesis as well as "concurrent clock-and-data" optimization.
• Day 3 topics include: More details on CTS setup; signal routing and post-route optimization; top-level integration and implementation using block abstracts; functional and timing ECOs, signoff DRC and metal filling using IC Validator.

Objectives

At the end of this workshop you should be able to use IC Compiler II to:

• Use the GUI to analyze the layout during the various design phases
• Control object and layer visibility, rearrange the GUI to suit your needs
• Perform timing analysis using the GUI
• Describe what elements an NDM cell library contains, and create an NDM technology-only library
• Use the Task Assistant to execute floorplanning steps as well as the place and route flow
• Create NDM reference libraries for use in ICC II, both for standard and macro cells, and for storing technology data (technology file, placement site and routing layer settings, RC TLU+ data)
• Create a block-level floorplan including automatic voltage area shaping and placement, automatic macro placement and advanced connectivity analysis, intro to pattern-based power network synthesis, macro keepouts and placement blockages, and congestion map analysis
• Perform and debug design setup to create an initial design which is ready for placement; this includes loading the netlist, floorplan- and scan-DEF files; Loading multi-voltage design data: UPF and voltage-area definitions; creating an NDM design library, and applying common timing and optimization controls
• Create modes, corners and scenarios for IC Compiler II’s rearchitected MCMM environment
• Use timing derate as well as AOCV and POCV derating
• Perform concurrent MCMM standard cell placement and related optimizations to minimize timing violations, congestion, and power; includes Design Fusion setup, leakage, dynamic and total power set up, layer optimization, spare cell handling, congestion-driven restructuring, route driving extraction (RDE), as well as embedded ICG optimization.
• Perform setup for clock tree synthesis and data-path optimization (define exceptions, targets, non-default routing rules, etc.)
• Execute the "classic" CTS and optimization flow, or the concurrent clock-and-data (CCD) flow; global and local skew optimization is covered
• Analyze clock tree and timing results post-CTS using the GUI and text reports
• Perform routing setup to control DRC fixing, via optimization, antenna fixing, and crosstalk reduction
• Route critical, secondary PG and signal nets and perform post-route optimization including post-CTS, CCD, power and crosstalk optimization
• Perform PrimeTime and StarRC based timing analysis and optimization within IC Compiler II
• Use ECO Fusion to perform timing ECO loops controlled from within IC Compiler II
• Create block abstracts and frame views for top-level assembly and implementation
• Analyze and fix physical DRC violations, using IC Validator from within IC Compiler II (In-Design Flow)
• Insert standard cell metal fillers and perform metal filling using IC Validator
• Perform functional unconstrained and freeze-silicon ECOs
• Generate all required output files for signoff extraction and static timing analysis in PrimeTime-SI
• Perform timing ECOs in combination with Primetime Physical Guidance

Audience Profile

ASIC, back-end, or layout designers who will be using IC Compiler II to perform placement, CTS, and routing on block-level designs

Prerequisites

While prior knowledge of IC Compiler II or IC Compiler is not needed, knowledge of general (non-tool specific) standard cell-based placement, CTS, and routing concepts and terms is helpful.

An understanding of basic digital ASIC design concepts is assumed, including:

• Combinational and sequential logic functionality
• Setup and hold timing

Course Outline – 3 days

Day 1

• Workshop Introduction and GUI use (Lecture + Lab)
• Objects, Blocks and App Options (Lecture only)
• Floorplanning (Lecture + Lab)
• Placement and Optimization (Lecture + Lab)

Day 2

• NDM Cell Libraries (Lecture Only)
• Design Setup (Lecture + Lab)
• Timing Setup (Lecture + Lab)
• Running CTS (Lecture + Lab)

Day 3

• Setting Up CTS (Lecture + Lab)
• Routing and Optimization (Lecture + Lab)
• Top Level Implementation (Lecture Only)
• Signoff (Lecture + Lab)
• Customer Support (Lecture only)

SNPS Tools Used

• IC Compiler II 2018.06-SP4
• PrimeTime 2018.06-SP2
• StarRC 2018.06-SP4
• IC Validator 2018.06-SP2

 

CustomSim

Overview

The CustomSim FastSPICE simulator delivers superior verification performance and capacity for all classes of design, including custom digital, memory and analog/ mixed-signal circuits. The comprehensive offering includes advanced analysis options for native circuit checking, power, signal and MOS reliability analysis and mixed-signal simulation.

Objectives

• Introduce FastSpice concepts
• Explain basic technologies and challenges
• Explain CustomSim benefits - PACE
• How to setup and invoke Customsim
• How to specity command or netlist option

 - Understand Netlist formats supported in CustomSim

 - How to control the speed-accuracy tradeoff

 - Navigate Interactive mode and Other useful commands

 - Explain CustomSim supported stimlus file formats

 - Explore CustomSim supported analysis commands

 - CustomSim supported post-layout flows

Audience Profile

Analog designers and engineers who perform circuit simulation and analysis at the transistor level.

Prerequisites

Analog Circuit Simulation

Course Outline – 2 days

• Introduction to Fast-SPICE
• Introduction to CustomSim
• Netlis Format Support
• Accuracy-Speed trade-off
• Newset_sim_level (SSL2)
• Interactive Mode
• Other useful commands
• Stimulus Format Support
• Analysis Support
• Post Layout simulation
• CustomSim-RA Simulation
• Log File

SNPS Tools Used

• 2019.06-SP2

 

FineSim

Overview

FineSim is a high-performance circuit simulator with built-in full SPICE and FastSPICE simulation engines. FineSim’s unique multi-core/multi-machine simulation capability allows users to drastically improve simulation performance and capacity. FineSim is well-suited for simulation of large, complex analog circuits, as well as DRAM/SRAM/ Flash memory design.

Objectives

PreparPrepare the students to use FineSim SPICE/PRO for analog simulation and analysis.

Audience Profile

Analog designers and engineers who perform circuit simulation and analysis at the transistor level.

Prerequisites

Analog Circuit Simulation

Course Outline – 2 days

Day 1

• Introduction to Simulators
• Introduction to FineSim & WaveView
• Invoking FineSim w/  Single & MCPU
• Simulation Controls - FineSim Spice
• Simulation Controls - FineSim Pro

Day 2

• Simulation Setup - Input/Output
• FineSim Back-Annotation
• FineSim Circuit Checks and Fscript
• FineSim Co-simulation
• FineSim IR-EM analysis

SNPS Tools Used

• 2019.06-SP1

 

SiliconSmart

Overview

SiliconSmart is the industry leading characterization and modeling solution to handle a wide range of IPs from standard cells to advanced I/O cells and embedded memories, including RAMs, ROMs, and register files. SiliconSmart supports industry modeling formats such as NLDM, NLPM, Liberty SI model, CCS models for timing, power and noise, ECSM models for timing and power, IBIS 4.1 modeling format, and AOCV timing models.

The class provides an introduction to SiliconSmart and the preliminaries of creating a setup to run characterization. It goes through a detailed explanation of the steps required to produce a final Liberty model starting with either netlists only or an existing Liberty file. Specifics of important configuration files along with discussions of the supported methodologies used for different measurements will also be covered.

The class will go through some advanced topics like Functional Recognition, User Defined Stimulus, Model API, AOCV and IBIS modeling. Guidelines will also be provided to troubleshoot and debug failures related to the setup, simulations, methodologies, or the circuit itself. The user will also be given an introduction to flow and setting modifications required for running other complex topologies and level shifters as well as a run through of the validation utilities available within SiliconSmart.

This class includes demos of comprehensive labs which provide an opportunity to apply key concepts covered during the lectures.

Objectives

At the end of this workshop the student should be able to:

• Invoke SiliconSmart and create a characterization point.
• Create global configuration and cell based instance files.
• Develop and run a complete flow for characterizing new cells or re-characterizing an existing liberty model at new PVT conditions or using new netlists.
• Update cell based instance file to apply settings for specific measurements and perform state dependent measurements.
• Control methodologies for measuring timing, power, leakage, capacitance, constraints and other arcs.
• Define functionality for simple, complex and custom cells, IO cells and memories.
• Define user configurable stimulus for custom cells.
• Perform post-processing on SiliconSmart generated Liberty models or independent Liberty files using Model API, which allows for large scale changes through minimal coding.
• Debug characterization and simulation failures.
• Run Validation utilities to compare Liberty models, as well as to perform data integrity checks on them.

Audience Profile

Characterization and Design Automation Engineers who will be using SiliconSmart to develop flows and to characterize standard cells, IOs, Memories and other complex cells.

Prerequisites

Basic knowledge of standard cell characterization and liberty modeling standard is desirable and helpful.

Course Outline – 2 days

Day 1

• Introduction and Overview
• Re-Characterization and Full New Characterization Flows
• Char-point Directory Structure and Important Configuration files
• Data Caching Mechanism
• Arc Selection and State Dependent Measurements
• Methods for defining Complex Cells
• Characterization Methodology for Level Shifters

Day 2

• •Characterization Methodologies for various SiliconSmart measurements
• •Debugging and Troubleshooting Failures
• •Validation Utilities
• •User Defined Stimulus
• •Model API
• •AOCV Modeling
• •IBIS Modeling

SNPS Tools Used

• 2019.06-SP1

 

CustomCompiler_SE_LE

Overview

Custom Compiler is a complete design platform including all functionality necessary to design custom digital, analog or mixed signal ICs

iPDKs are supported out-of-box

Custom Compiler provides options to customize every component of the tool including the UI, preferences and additional procedures. In this way, the existing functionality can be extended to support any given design flow

Objectives

• Use a standard Custom Compiler components library
• Create and place Instances
• Edit Instance parameters
• Add pins
• Wire the design
• Name the nets
• Check the schematic for errors
• Define and use grids
• Navigate in the layout
• Use the Object Layer Panel
• Create shapes using data creation functions
• Edit shapes using data editing functions
• Use clipboard commands
• Initialize SDL
• Understand SDL Elaboration
• Use different rules to change SDL Elaboration

Audience Profile

Analog Layout engineers who perform physical implementation

Prerequisites

Analog Layout experience

Course Outline – 3 days

Day 1

• Custom Compiler Overview
• Library Manager
• Data IO
• Schematic Entry
• Advanced Schematic Editing
• Symbol Creation
• Working with Text Views
• Expression Languages
• Design Hierarchy
• Hierarchy Configuration
• Data Setup and Simulation
• State Saving Loading
• Corner Analysis

Day 2

• Layout Design Entry
• Abutment and Align Functions
• Layout Advanced Editing Functions
• Hierarchical Design Creation
• Connectivity Engine
• Design Rule Aware Editing
• SDL-Initialization and Elaboration
• SDL-Placement with Connectivity Use
• SDL-ECO and Cross Object Referecing
• SDL-Placement Advanced
• SDL-Symbolic Editor

Day 3

• VAA-Introduction
• VAA-Build-in Template Library
• VAA-Placement Constraint Description
• VAA-Pattern Router
• VAA-Template Manager
• Electrical Checking and Reporting
• EM Checking and Reporting
• Resistance Checking and Reporting
• EM Aware Layout Implementation
• Capacitance Reporting
• Router-Interactive Router

SNPS Tools Used

• 2019.06-SP1

 

MSV

Overview

The complexity of mixed-signal system-on-chip (SoC) designs is rapidly increasing due to growing analog content, advanced analog and digital interfaces and tougher requirements for safety and reliability. This is driving a crucial need for advanced verification methodologies and technologies. Synopsys’ VCS AMS mixed-signal verification solution, incorporating VCS functional verification and the CustomSim FastSPICE simulator, delivers advanced functional and low-power verification technologies combined with class-leading performance and capacity for faster mixedsignal SoC regression testing.

Objectives

At the end of this workshop the you should be able to:

• Understand concept of MSV
• Understand the reports file generated by MSV sim.
• Run MSV simulation & Debug

Audience Profile

Design or Verification engineers who perform analog/logic simulation and analysis

Prerequisites

Logic / analog simulation experience

Course Outline – 1 day

• Introduction to MSV
• Setup Files
• Interface Elements
• Cross Module References
• Save and Restore

SNPS Tools Used

• 2019.06-SP1