StarRC VMF vs. IC Validator AMF Positioning: Balancing Chip Performance

Nitin Kalra, Sr. Manager, Applications Engineering from Synopsys, will discuss how metal fills play a substantial role in deciding the performance of chips and reliability. Designers ultimate goal is to balance the effect of metal fill on performance without sacrificing reliability. This balancing act results in a highly iterative process and use of the Actual Metal Fill (AMF) tool for ECO phase increases the turnaround time. Instead the Virtual Metal Fill (VMF) tool can be used during the ECO phase and the design can be brought to the Signoff level where the AMF tool can be used. StarRC VMF results correlate well with IC Validator AMF results, further increasing design flow efficiency.

Transcript:

In this short video, I'm going to discuss the StarRC Virtual Metal Fill feature and how it can benefit your design flows. Faster time to market is the paramount goal for any chip design company, and EDA tools are designed with this metric in mind. There is an ever-increasing need for reducing overall turnaround time for a typical design cycle. One of the key steps of digital design flow is Metal Fill insertion.

There are guidelines from foundries to meet mandatory target density per metal layer that must be followed to achieve reliable fabrication and high yield. As shown in the graphic, traditionally the Signoff or ECO flow included Metal Fill insertion using foundry-provided IC Validator runsets. Fill is inserted as part of the NDM or DEF database, which is consumed by StarRC to generate SPEF files with Signoff-quality Interconnect Parasitics, which is then used by PrimeTime for accurate timing analysis.

The Fill insertion step takes a finite amount of time, which can vary from minutes to hours depending on the block size, sparsity of the block, among other parameters. StarRC's Virtual Metal Fill feature can help reduce turnaround time through on-the-fly Virtual Metal Fill insertion and extraction. This feature can be used during ECO flows, whereas IC Validator-generated metal fill can be used during final runs for signoff. The runtime overhead for virtual fill insertion and extraction is negligible, providing noticeable runtime savings for the overall ECO loop, resulting in faster design closure as shown in the graphic.

StarRC's Virtual Metal Fill feature is very flexible in terms of input data as well as usability. It can directly read the ICV runset to get the fill parameters, or it can generate a golden parameter file based on signoff fill inserted in the design. There is on-the-fly detection of NDR rules applied to the net, and fill insertion is done while ensuring the NDR rules are not violated.

Users can also specify their own set of critical nets and the corresponding fill insertion parameters through the parameter file. There is also flexibility to specify the cells to be excluded from fill insertion for hierarchical fit methodology. That is, you can mix and match between signoff fill and virtual fill in the same design.
As shown in the table, in terms of accuracy, the VMF feature provides tight correlation between signoff-level data in terms of mean and standard deviation.

In conclusion, adopting StarRC Virtual Metal Fill in your design flow provides you with faster ECO turnaround time and signoff-correlated accuracy with no setup overhead.

Thank you.