How Renesas Utilized Synopsys for a 30% Increase in SoC Verification Productivity

Taruna Reddy

Mar 11, 2024 / 3 min read

You’ve probably seen firsthand the advancements in automotive systems driven by autonomous driving on your local roads. The integration of technologies such as 5G networks and artificial intelligence (AI) has enabled self-driving cars to perform better than ever before, but new, strict safety standards add an additional layer of consideration.

These developments come with added silicon complexity and often unseen changes in the system-on-chip (SoC) design requirements — like re-architecture (specifically in-vehicle electrical/electronic [E/E] architecture from the traditional controller area network [CAN]), introduction of in-vehicle Ethernet, higher speeds, and real-time control compatible with various standards. Verifying these complex SoCs can take up to 70% of the project cycle and involve many more engineer hours! 

Renesas, a global leader in microcontrollers, analog, power, and SoC products for applications such as automotive, industrial, and information technology (IT), encountered this very challenge and aimed to reduce that by 50% by leveraging Synopsys™ (Verification Space Optimization), an AI and machine learning-driven verification space optimization technology. 

soc design verification

Renesas’ Verification Challenges

Especially in the automotive market, time-to-market pressures can be very demanding. That’s why the Core IP Division at Renesas was exploring different ways to automate the coverage closure phase in their verification cycle. Engineers were experiencing a range of different challenges including manual analysis and triage to determine un-hit coverage and ensure that the product was ready for use and verified thoroughly for any logic or functional problems. All of this had to be done within a certain compute budget for each IP/project.

Closing the ‘last mile’ of coverage involved developing directed tests targeted for the un-hit coverage. Instead of the manual process of writing directed tests to close coverage holes that might result in running thousands of regressions with unknown return on investment (ROI), Renesas was eager to try something novel by leveraging AI/ML technologies, which led to their interest in Using machine learning, regressions are optimized in so that high ROI tests are run first, and analysis is automated to define prescribed insights.

Renesas’ Compelling Results with

After observing positive results with, implementation was easily facilitated due to Renesas’ current use of Synopsys VCS® functional verification solution. Without requiring any modifications in the design or testbench code, integrates within existing VCS regression environments. 

As highlighted at SNUG Japan 2023, Renesas was able to use fewer directed tests, experience shorter regressions for the same coverage, and improve the root-cause analysis of un-hit coverage by using Without having to conduct manual analysis of huge datasets, Renesas took advantage of to help their verification engineers reach coverage targets faster. This enabled running more regressions within the same compute budget, leading to better hardware utilization and uncovering of bugs earlier, which is the ultimate goal of verification.

The end results speak for themselves:

• Higher quality of results (QoR) from improving coverage by up to 10% using the same number of tests

• Reducing regression test list by 2x

• Reducing coverage holes by 90%

The figure below highlights key use cases for the solution. 

functional soc verification tools

“Meeting quality and time-to-market constraints is fast becoming difficult using traditional human-in-the-loop techniques due to the ramp in design complexity,” said Takahiro Ikenobe, IP development director, Shared R&D Core IP Division at Renesas. “Using AI-driven verification with Synopsys VCS, part of the EDA suite, we’ve achieved up to 10x improvement in reducing functional coverage holes and up to 30% increase in IP verification productivity, demonstrating the ability of AI to help us address the challenges of our increasingly complex designs.”

Instead of spending endless amounts of time writing directed tests that slow time to market and may still lead to bug escapes, the Renesas engineering team is now able to focus on design innovations and higher value programs while still beating competitors to market. is a vital part of the AI-driven EDA suite that improves efficiency throughout the entire EDA flow to handle the increased design complexity that the market demands, decrease manual labor, and harness actionable insights that can be collected throughout the entire development of silicon. 

To learn more about, register for SNUG Silicon Valley 2024 to attend a technical session presented by NVIDIA: Reducing Manual Effort & Achieving Coverage Goals with Synopsys, ICO, & VCS-UNR.

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