A New Approach to SoC Design with Silicon Lifecycle Management

Why is SLM Necessary?

In industries where silicon performance and reliability are critical — such as high-performance computing, data centers, autonomous vehicles, transportation and industrial IoT — quality, security and reliability are growing concerns that cost companies billions of dollars to monitor and address. Much of the challenge is directly related to the complexity of today’s electronics systems driven by advanced manufacturing processes and massive integration. This, coupled with a rapidly decreasing tolerance for system failures or service interruptions, has driven us to look at a new approach based on our proven strength in design and test. Our approach extends beyond those initial stages of a chip’s lifecycle to address how silicon-based systems are developed and maintained. With the SLM platform, our focus is on the delivery of a solution to better manage each phase of a chip and system’s lifecycle from development through end-user deployment to ensure optimized results and lower risk throughout the process.

“Addressing critical chip performance and reliability issues is a multi-billion-dollar issue that doesn’t stop at tape out. It requires a new way of looking at the entirety of how an IC is designed, built and used. Providing access to device data throughout the entire chip life span, and enabling ongoing ‘in life’ feedback and optimization through specialized analytics will allow a more efficient and effective way to address the semiconductor-related quality and security challenges system companies face in all industries,” noted Richard Wawrzyniak, principal market analyst, ASIC & SoC, Semico Research Corp.

First, non-intrusive monitors and sensors that are embedded throughout each chip gather as much useful data about each chip as possible. This provides visibility into all forms of circuit activity as well as environmental conditions like voltage and temperature.

Automated integration of the monitors and sensors into the RTL or gate-level design is provided through the Synopsys TestMAX™ test integration solution which when coupled with the Fusion Compiler™ RTL-to-GDSII solution for synthesis and physical implementation, ensures the monitors are integrated while maintaining optimal power, performance, and area (PPA) design metrics. The SLM platform links TestMAX™ to Synopsys’ signoff analysis tools for guidance on where to optimally place the monitors and sensors.

Second, analytics on the chip data obtained from the monitors and sensors enable optimizations at each stage of the semiconductor lifecycle, starting with design implementation, and progressing through manufacturing, production, test, bring-up and culminating with in-field operation. The SLM platform includes several targeted analytics engines. PrimeShield closes the loop on design implementation by leveraging both silicon data-based timing model calibration to minimize required margins as well as advanced analytics to further optimize design PPA, reliability and silicon predictability. The SiliconDash™ semiconductor manufacturing analytics engine and the Yield Explorer™ design yield analysis engine use fab and test data enhanced with monitor and sensor data to optimize manufacturing and test operational efficiencies as well as improve overall yield. The platform also features two additional analytics engines, an Adaptive Learning Engine and an Embedded Learning Engine, that enable optimized test bring-up and introduce self-analysis and predictive maintenance capabilities during the in-field operation of the chip.