Cloud native EDA tools & pre-optimized hardware platforms
In this video Sahil Bargal, Applications Engineer, Synopsys, will give a brief overview of Synopsys' PrimeShield solution.
Thank you for joining us for the first of our 4-part video series on PrimeShield design robustness analysis and ECO. Today, I'm going to be joined by Sahil Bargal, the PrimeShield applications engineer at Synopsys. Today Sahil is going to be giving us a brief introduction on PrimeShield. Take it away, Sahil.
One of the main problems we are dealing with at advanced tech nodes is the increase in process and voltage variation that makes it challenging for the design teams to ensure robust product functionality as well as performance. This is exactly where PrimeShield comes in. PrimeShield is comprehensive timing robustness analysis and helps to increase the robustness of the design at the design level, individual part level, or cell level by identifying the bottlenecks in the design and doing targeted fixing of those bottlenecks.
In this process, PrimeShield helps to minimize over-pessimism, over-margining, and over-designing.
PrimeShield is built on golden timing engines in PrimeTime and the fundamental ability to perform STA-based Monte Carlo analysis. This highly optimized STA-based Monte Carlo engine enables advanced analysis of process and voltage variation and its impact on timing.
PrimeShield also provides an ECO option using the fixed ECO robustness command, which targets timing-critical or IR-critical weak cells to improve the overall robustness of the design. This can then be measured using various metrics like improvement in FMAX, reduction in high sigma failure rate, improvement in voltage robustness, and all these benefits with very little impact on power and area.
The fundamental requirement for most PrimeShield features is to have POCV LVF libraries, and voltage robustness features require voltage scaling libraries. Fast Monte Carlo simulation requires HSPICE models and netlists as well.
One of the key challenges to statistically analyze design level robustness is the ability to look beyond a single WNS value of the design. Having an accurate methodology to determine a distribution of WNS values based on worst endpoints is important. If all the endpoints have a 3 sigma slack greater than 0, then we consider the design to be meeting timing. However, due to high variation in the design, we may not be at the 3 sigma level at the design level even when all the paths pass 3 sigma individually. So, the design success rate is lower than 3 sigma, and design teams try to work around this by signing off at higher sigma or by adding a lot of margins or timing delays, which lowers the PPA of the design, lowering the performance of the design and increasing power consumption.
An approach that looks at the timing-critical paths in the design may not be sufficient, and the design team may need higher coverage in the design. An approach that also looks at all the cells in the design is required so that we can use that to improve the overall robustness of the design.
The solution to these challenges can be addressed by a feature that performs Monte Carlo analysis at the STA level for advanced timing and voltage variation analysis, while considering the topological correlation between the paths to avoid pessimism. Monte Carlo STA is equivalent to doing a lot of STA runs with different samples. Each Monte Carlo sample is one STA run or one virtual chip. Each virtual chip has one WNS from its worst endpoint slack. If we have 100,000 virtual chips generated by STA Monte Carlo, we will be able to generate a design level WNS distribution. By considering all the paths together and creating a design level WNS distribution, we can determine the joint success rate of the design. With the design slack distribution, we can also derive the frequency distribution of these virtual chips, as shown in the histogram on the right. This frequency distribution clearly shows how many virtual chips met the target frequency.
Thank you, everyone, for joining us today. Please stay tuned for the next video of this 4-part series where we will go into PrimeShield's feature highlights in more detail.
Quickly develop advanced digital, custom, and analog/mixed-signal designs with the best power, performance, area, and yield.