Samsung Foundry Accelerates Billion-Gate Low-Power Signoff with Synopsys VC LP

Avinash Palepu, Chiragkumar Patel

Jan 18, 2024 / 3 min read

For today’s mobile and high-performance systems, low-power design is essential. Such designs are more sustainable, translate to longer battery life, create better seamless consumer experiences, and reduce energy costs. All these benefits aside, reducing power consumption is a challenging task for chip designers and verification/RTL engineers. Next-generation SoCs are expected to be 10x larger, and low-power signoff for some designs can take as long as a couple of days. Clearly, an advanced low-power verification solution is needed to help engineers validate complex low-power structures within a reasonable turnaround time.

One such solution is Synopsys VC LP™ Advanced static low-power verification solution, which has successfully passed Samsung Foundry’s certification process. As a static checking product, VC LP Advanced technology effectively addresses the complexity of validating low-power designs, streamlining and expediting the debugging process.

low power soc design verification

“By employing the Synopsys VC LP Advanced solution at RTL, post-synthesis, and post place-and-route stages, Samsung was able to achieve billion-gate 5nm low-power mobile design signoff and detect low-power bugs earlier and more efficiently than with conventional methods,” said Jianfeng Liu, principal engineer in the Design Technology Team, Samsung Foundry. “The simulation process can now identify dynamic low-power issues more efficiently thanks to multithreading, resulting in a runtime that is approximately twice as fast. Additionally, the Signoff Abstraction Model (SAM) flow brings significant runtime reduction for full-chip, top-level verification. These have saved countless engineering hours and allowed our verification team to focus on more high-value tasks.”

low power chip design verification

How Power Management Techniques Impact Chip Design Verification

Samsung’s low-power designs used the highly sophisticated low-power SoC design techniques. While these techniques allow for fine-grained power management, they also add complexity to the design and verification processes. Some common low-power techniques in Samsung Foundry designs are listed as below:

  • Power Gating & Isolation: The power gating technique implements power switches into the IC design, which requires isolation gates that clamp the boundaries of the power domain to known values when off. A power management unit controls the power switch and isolation by enabling signals to ensure that values during shutdown are clamped to the right values at the right time.
  • Retention: Retention is another technique used along with power gating. In each shutdown block, when the block is off, either a subset of the flops or all the flops in the block have their previous values saved. When the block powers on, then the previously saved values are restored. This saves power by reducing the time and steps necessary to get the saved state, as well as improving the overall ramp-up time to restore the previous functionality of the block.
  • Level Shifter: Multi-voltage designs require designing in separate voltage islands, meaning that voltage crossings between islands may require “level shifter” cells that implement and analyze the blocks at their different voltage characteristics.

The intricacies of low-power SoC design architectures and elements, such as those discussed above, pose greater challenges for chip verification and approval compared to always-on SoC designs. In fact, SoC-level low-power signoff is orders of magnitude more complex than IP-level verification. This stems from the complexity of design sizes, hundreds of power domains, and millions of low-power states that need to be verified. Additionally, there are the architectural complexities that arise from IP integration, such as functional feedthroughs, feedback loops, and segregation of reports based on IP ownerships.

low power soc verification

This complexity is effectively addressed by a static checking solution, such as VC LP Advanced technology, which streamlines and expedites the debugging process. Instead of debugging a very noisy report, Synopsys VC LP Advanced has a machine learning root-cause analysis (ML-RCA) function that allows the software to point to the root cause of an issue that takes care of errors in other lines of the report. This function essentially boils down a large number of violations to cluster with root-cause details. With this insight, users can start debug with the cluster, rather than having to go through each violation one by one. VC LP seamlessly scales to address the SoC-level complexity, capacity, and performance requirements and enables a speed-up in low-power signoff from RTL to power grid netlist.

Ultimately, Samsung Foundry accomplished first-pass silicon success and on-time product delivery for the highly sophisticated billion-gate 5nm mobile low-power chip with the assistance of the machine-learning-enabled and high-capacity VC LP Advanced solution.

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