Leveraging Early Power Network Analysis to Accelerate Chip Design

IR drop is becoming a critical issue for today’s designs. It refers to the drop in voltage (V) caused by the increase in wire resistance (R). The need for greater functionality in ever-shrinking geometries impacts power distribution to the chip. Fabrication technologies have become smaller to pack more transistors on to a chip while the size of the wires that deliver power throughout the device is also diminishing.

However, the physical chip dimensions are staying roughly the same. The result is that wires have become thinner but not shorter leading to an increase in resistance per unit length. Designers can expect nearly a 10x increase in resistance between a 28nm chip and a 7nm chip with an exponential increase for even more advanced process nodes. But the total power consumed by a chip remains flat.

Delivering power throughout a semiconductor device must be well planned so that functionality and performance isn’t lost or broken. This is especially true for companies like MediaTek who produce more than two billion devices each year and whose devices are integrated into one of every three cell phones.

Early Power Network Analysis to Combat IR Drop

MediaTek outlined how they solved the challenges associated with IR drop at the Synopsys User Group (SNUG) conference held in Japan. The team implemented what is known as power network analysis (PNA) to ensure that enough power is delivered to each transistor to mitigate potential power-related issues within the chip. PNA considers factors like power grid topology, current flow and power supply to evaluate the PDN’s performance. But applying PNA must be done early. Later stage signoff IR analysis can lead to significant re-design delays and increased costs. However, applying PNA early can help designers identify power-related issues like excessive voltage drop and excessive current density in time to modify the delivery network so as not to disrupt time-to-market goals. Performing PNA early allows designers to optimize the PDN instead of reacting to signoff surprises which can lead to tedious engineering change order (ECO) loops. For example, early analysis can let them know that power or ground connectors must be added or that the routing and wires sizes must be adjusted. Performing this early analysis allows for the ability to efficiently co-design to minimize turn-around-time.

To perform and integrate early PNA into the design flow, MediaTek adopted Synopsys IC Compiler II with Red Hawk Fusion. The solution helped to handle complex power domains, power grid extraction, and current source modelling to achieve an accurate IR analysis. Based on the analysis, the team was able to generate a voltage drop map to identify and address potential issues with the power grid early. Had MediaTek performed traditional late-stage signoff IR analysis, power violations would be detected too late in the process requiring many more design iterations that each would require days to optimize. Through early PNA, MediaTek was able to fix violations as they were identified reducing optimization time to one day. Early PNA using Synopsys IC Compiler II resulted in a 90% reduction in IR violations. IR drop improved from 20.92% to an impressive 2.1462% with a 95% signoff accuracy.

In another example, Microsoft described their usage of Red Hawk fusion in the recent Synopsys User Group (SNUG) in Silicon Valley. Their challenge was manually fixing IR drop issues post-route on large, complex designs with billions of nodes in their power network. In the traditional flow, IR fixing is done after route has completed and timing has converged. IR analysis indicates a failure, so they perform an ECO to fix the problem which often disturbs timing and other design QoR leading to more ECO loops. They needed a flow that addressed IR drop earlier during place and route optimization but would not degrade the timing or cause new DRCs.

To address this challenge, Microsoft used the Red Hawk fusion IR Driven Placement (IRDP) flow. IRDP was enabled during post CTS optimization. Sigma DVD analysis was done to generate the voltage drop (static and dynamic) for victims and aggressors. The IR information was used by the IC Compiler II optimization engine to spread or relocate cells experiencing high IR drops. IRDP resulted in 0 Static IR violations and a 67% reduction in Dynamic IR violations in IR signoff verification. The TNS showed a negligible 1.7% degradation. 

The heat map below shows what happens before and after an IR drop fix. 

IR drop heat map, showing before and after fix perspectives.

MediaTek and Microsoft’s use of Synopsys IC Compiler II is a prime example of how adopting early power network analysis can provide a comprehensive view of the power delivery network so that power-related issues can be corrected as they are identified early in the design process. This helps to reduce costly time-consuming design iterations and improves co-design efforts by shifting the IR drop profile to the left. Dramatically reducing overall turn-around-time enhanced the ability to meet ever-shrinking time-to-market windows. MediaTek is already adopting this same strategy for its more advanced process node projects ensuring that their devices will meet the demands of today’s market.