Fault Simulation Techniques for Safety-Critical Chip Designs

Kirankumar Karanam, Rimpy Chugh

Sep 13, 2022 / 2 min read

Faults happen, but this doesn’t mean that you can’t prevent them from hampering performance or causing some other unintended behavior in your chip designs. From cars to medical devices and aerospace equipment, safety-critical electronic applications carry too much impact to be brought down by issues such as semiconductor aging effects or an alpha particle hit. Imagine having a vehicle that doesn’t stop when the driver (or self-braking feature) applies the brake, or a pacemaker that stops working properly.

To ensure that faults can be detected and corrective actions are taken in a timely manner, functional safety standards play a critical role in the design process for chips that bring so many of our essential systems to life. Standards like ISO 26262 for road vehicles or IEC 61508 for general industrial safety prescribe a development process for designers to document and follow to ensure that components do what they’re intended to do. Corrective actions could include system resets to repair faults or error correction techniques.

Air Force cabin during a flight

Fault Simulation Techniques

Fault simulation presents one of the most efficient ways to evaluate the impact of faults in the field and ensure that designs will respond in an appropriate way. It’s often done after the design has been through functional simulation. At this point, there ideally shouldn’t be many changes. While the process involves assessing all potential failures in a design and determining whether they can be detected, fault simulation success is impacted by the diagnostic coverage goal. The more safety-critical the design, the higher the diagnostic coverage goal. With larger, more complex chip designs, this process only becomes more difficult and time-consuming given the number of fault simulations that are needed to meet the goal.

The need to comply with functional safety standards for safety-critical designs has been known to add up to 30% to the functional verification effort, of which fault simulation is an integral part. Many traditional fault simulation tools and methodologies simply aren’t up to the task.

Fortunately, there is now a solution that integrates functional verification and fault simulation into a single flow. The Synopsys Unified Functional Safety Verification Platform is well suited for the large, complex SoCs that are increasingly common for applications like automotive, military, medical, and more. A key component of the platform is the Synopsys VC Z01X next-generation fault simulator, which ensures that verification teams can progress from functional simulation to fault simulation with minimal changes in setup, design or testbench code, or debug methods.

New Technical Paper

Our new technical paper, “Ensuring Functional Safety with Advanced Fault Simulation,” discusses key considerations for safety-critical applications and explains how our Unified Functional Safety Verification Platform helps produce reliable chips that meet functional safety standards as well as time-to-market targets. Read the paper today for insights on how you can prevent in-field faults from leading to potentially devastating outcomes.

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