CXL 3.1: How Evolving CXL Standards are Pushing Interconnects to Even Higher Performance

The journey from CXL 2.0 to CXL 3.x marks significant progress in addressing industry demands. One of the primary drivers behind the evolution to CXL 3.x is the need for higher speeds, aligning with PCIe 6.x. Additionally, there's been a shift toward a more symmetrical coherence model, allowing devices connected to CXL to generate memory cycles and communicate more effectively with each other. This enhancement facilitates a more versatile and efficient use of memory across different devices, moving beyond the traditional host-centric approach​​.

One thing has remained constant: CXL continues to be a pivotal interconnect technology enabling efficient, high-performance communication between CPUs, accelerators, and memory devices. The latest CXL 3.1 specification addresses the growing needs of data-intensive applications in next-generation computing.

Key Features of CXL 3.1

CXL 3.1 marks a significant step forward in interconnect technology building on CXL 3.0, offering enhanced speed, security, flexibility, and efficiency necessary to meet the rapidly increasing industry demands. More specifically, CXL 3.1 offers the following improved features compared to its predecessors:

• Extended Meta Data: Supports up to 32-bits of meta data per cacheline and 2-bits of meta-data for cache coherency that describe if a cache line is shared, exclusive, modified, or invalid. 

• New Use Cases: New information gleaned from meta data allows for use cases such as access control, data type tagging, memory-tiering algorithms, and more.

• Improved Visibility into CXL Memory Device Errors: Provides new information on correctable error limits, the source of the errors, and the transaction occurring during the error condition.  

• More Control Over Memory Device RAS: Offers memory sparing, DDR5 error-check scrubbing, media testing, patrol-scrub, and information on capacity/performance degradation.

• Trusted Execution Environment Security Protocol (TSP): Enables virtualization-based TEEs to host confidential computing workloads.

• Peer-to-Peer Communication: Facilitates direct peer-to-peer CXL memory access for accelerators, improving resource utilization and reducing latency.

While all these features are true enhancements, CXL 3.1 introduces more complexity and, therefore, new challenges. With the release of any new standard, addressing these challenges is crucial to ensure stability and performance. For instance, CXL 3.x has adopted a 256-byte flit format to enable forward error correction, similar to PCIe 6.x, to mitigate bit errors. This change is pivotal in maintaining data integrity and performance at higher transfer rates​​. 

Security remains a cornerstone of the CXL 3.1 standard. Specifically, the Trusted Execution Environment Security Protocol (TSP) applies to CXL.cache and CXL.mem, and is designed to secure virtualization-based environments, enabling them to host confidential compute workloads. This feature builds on the existing Integrity and Data Encryption (IDE) protocols introduced in CXL 2.0, further enhancing data protection across the interface. TSP's integration ensures that data remains confidential and intact, safeguarding against potential security threats in virtualized environments which is even more important today as data becomes more sensitive and regulations become more strict​​. CXL.io virtualization support continues to be governed by the TEE Device Interface Security Protocol (TDISP), released in August 2022, managed by PCI-SIG.

These security protocols collectively enhance protocol-related security. Synopsys’ expertise in these areas enables us to provide comprehensive support and ensure that our implementations are both robust and secure.