Why Analog Design Challenges Need Breakthrough Technologies

Synopsys Editorial Staff

Apr 30, 2024 / 5 min read

As demand for semiconductors continues to rise, analog IC design engineers are struggling to solve great challenges including migrating analog IP across technology nodes and achieving new power and performance metrics that, for so long, seemed impossible. Increasingly, AI technologies are helping the industry solve what used to be unsolvable tasks. Can the same be applied to the analog side of designs?

At this year’s SNUG Silicon Valley 2024 conference, technology leaders shared their perspectives during a panel discussion, “Unsolvable Analog Design Challenges Need Breakthrough Technologies.” As analog designs march toward angstroms, design rules become more complicated. New transistor devices, such as FinFETs, gate-all-around (GAA), and complementary FETs (CFETs), present fresh challenges, as do multi-die designs with their vertical architectures. 

Amidst a serious talent shortage, analog design teams must figure out how to run design rule checks and simulation, how to address parasitic effects and electromigration/IR drop (EMIR), and much more. And while the digital side of the house tends to get a lot of focus, today’s designs continue to contain plenty of analog components, from high-bandwidth memory to high-speed I/Os.

With Alessandra Costa, SVP of applications engineering at Synopsys, moderating, the panel dove into these topics and more. The participants were:

  • John Lee, GM and VP of Electronics, Semiconductors and Optics, Ansys

  • Rachid Salik, director, TSMC

  • Ting-Sheng Ku, senior director of Engineering, NVIDIA

  • Huijuan Wang, senior director, Western Digital

  • Sridhar R. Boinapally, senior director, Analog Mixed Signal Tools/Flows, Intel

Read on for insights about specific challenges faced by the analog community and how breakthrough electronic design automation (EDA) technologies can bridge the productivity gap, particularly at advanced nodes. 

analog ic design tools snug 2024 panel

What Keeps Analog IC Design Engineers Up at Night?

One of the main challenges in the analog world is the manual effort required to complete a design. For example, Western Digital has a global layout team spread across three sites. Said Wang, “We work 24 hours, almost 24/7, just to redraw all the layouts for a new technology node, which is a huge effort. We cannot keep up with the complexity of the design if we keep doing things manually. So right now I feel it’s an exciting time with AI. We’re eager to work with Synopsys to develop better tools for the design community.” 

Ku pointed out that, when analog teams discuss bringing in automation or other tools, “the ROI calculation is never that great. So on one hand, the analog problems are harder to solve to begin with. So it requires more resources to create automation, to create workflows that help the analog designers. But on the other hand, the payoff is .. ‘Oh, you are only occupying…10% of the die space?!”

Continuing his thread, Ku did strike an upbeat note, “I think by default, with analog design automation, it’s not going to be the first one to do because it’s harder and the return on investment is lower. But eventually, we’ll get there.”

While analog is a very complex domain, Salik believes that there is nothing the ecosystem cannot do. “Time to market is pressuring everybody, both on the digital side and as well as the analog side,” he said. “From the TSMC side, we’ve recognized that this is a big opportunity, a challenge but it’s a big opportunity for us to do a few things to enable how we can design analog faster. We recognize [analog] is a big interest for our customers, and we’ve developed quite a bit of capabilities, tools, and methodologies, and have validated them, moving from planar to FinFET and now from FinFET to GAA, or nanosheet, as we call it.” 

Boinapally offered a slight contradiction to Salik’s perspective. “I think in IP reuse or design migration, the electronic design offerings today are not up to the mark. A lot of times in the design, we’re mostly migrating an IP from one process node to the other…and, in our case, from one foundry to another as well. And most of it is manual. Regardless of what people say, everything is manual…the layout, even the schematic migration. Yes, some of it is automated, but a lot of it is done manually, even basic stuff like design centering.” As such, Boinapally contends there are “huge opportunities. I see a big, big way to improve our productivity, and design migration would be one of them.” 

Lee highlighted some of the opportunities he sees for automation in the analog space. Looking at CFETs as an example, he noted the tremendous thermal effects inherent in these devices. Also important in any type of high-speed analog design are the electromagnetics and parasitics. “There’s tremendous opportunity to simulate those parasitics, those physics,” Lee said. “But it’s important also that this be done in a way that can root cause the source of problems and give you the tools to do optimization.”

What’s Needed for Multi-Die Chip Designs and Beyond?

With multi-die designs becoming more prevalent, particularly for compute-intensive applications, Costa was interested in how the companies represented by the panelists are addressing related challenges. Salik noted that TSMC is investing heavily in 3DIC technologies, working closely within the ecosystem. “This is an industry where we like the challenge,” he said. “And once we identify a challenge, we get together and try to solve it. So there are many initiatives in that aspect that TSMC is doing with EDA for the enablement, and also the optimization, of 3DICs.”

Ku noted that he has seen tremendous growth in simulation usage at NVIDIA, noting: “I feel that we are at the point where, perhaps, we want to speed up stuff. In addition to that, there needs to be more investment in simulating smarter. Perhaps simulate only the critical areas.” 

Lee called for development of an analog constraint language that conveys what the engineer intends to do. He explained, “If it deviates by more than this, then tell me. And when you tell me, tell me why.” Adding to this, Salik pointed out the importance of incremental actions that he’d like the EDA community to explore, “My understanding of what we are doing is, not only the design intent, but once you simulate and you do a change, you need to have a memory of what has been done and try to leverage whatever has been done to not redo it again.” In his perspective, this can be another opportunity for AI: to assemble a whole design flow and capture what has been changed and what has not been changed.

How Can AI Address the Engineering Talent Shortage?

Amidst the challenges, the engineering talent shortage also looms large. As Costa noted, “The gap between what is needed from a resource standpoint and what we have or what our colleges can produce is increasing. And I can tell you that having run field engineering for more than one company, finding good engineers is not that easy. So how can we help mitigate the talent shortage that we have? There’s promising innovation in AI.”

The panelists discussed the importance for engineers to engage in self-learning, and pointed out how tools like ChatGPT can support this, while AI co-pilots can help with faster ramp up for new engineers. 

Boinapally emphasized that the industry is trending toward having fewer people with true knowledge of analog design. He wondered if the EDA community could increase the abstraction of its tools, flows and  methods. A higher level of abstraction coupled with AI could potentially help newer engineers be more productive right from the start. “I believe that’s possible, to abstract our problems better. I think that’s where we should invest.”

Closing the panel discussion, Costa noted, “What I walk away with is that progress has been made, but there is still a long way to go. And maybe AI is going to help.” 

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