Explore challenges and solutions in AI chip development
Synopsys was recently recognized as the 2025 Technology Innovation Leader for Analog In-Memory Computing by Frost & Sullivan, underscoring its leadership in AI-powered analog and mixed-signal (AMS) EDA solutions. This recognition reflects Synopsys’ strategic focus, continuous innovation, and deep collaboration with customers to address the evolving demands of semiconductor design. As modern chip architectures become increasingly analog-aware—driven by the need for ultra-high-speed data movement in AI training, V2X communication in automotive, and high-performance RF in 5G and IoT—the role of analog design has become mission-critical. With analog content embedded in nearly every advanced system, the pressure to deliver accurate, efficient, and scalable AMS designs has never been higher. Synopsys delivers a modern, integrated AMS design platform that is purpose-built to meet these demands, setting the stage for the key challenges and breakthrough solutions that follow.
Modern chip designs are dominated by AI, connectivity, and automotive trends – all of which place new demands on analog front-ends and mixed-signal IP. AI training and inference require “tsunamis” of data to move between compute nodes 1 . Hyperscale data centers and AI accelerators depend on ultra-high-speed I/O to meet growing bandwidth demands. To support this, next-generation SerDes PHYs, capable of 100 Gbps per lane and beyond, are essential ². In fact, the bandwidth needs of generative AI and large language models are pushing SerDes standards from 56G/112G into 224G and beyond ². Each doubling of SerDes speed adds huge challenges in signal integrity and analog design.
Meanwhile, automotive and IoT growth is pushing analog integration. Connected and autonomous vehicles use multiple sensors (radar, LIDAR, cameras) and support V2X (vehicle-to-everything) communications over 5G/C-V2X. These systems require RF front-ends, high-speed ADCs/DACs, and custom PHYs, driving more analog/mixed-signal SoCs ³. In mobile and wireless markets, 5G/6G RF transceivers and Wi-Fi 6/7 components continue expanding, further swelling analog IP demand.
In short, virtually every modern application – from AI to automotive to wireless – needs sophisticated analog and AMS designs. This confluence of trends is creating an unprecedented surge in analog design complexity and volume, placing analog back at the center of innovation.
Analog design today is labor-intensive and fraught with difficulty. Analog circuits are highly sensitive to process variations, temperature and parasitics; each device’s performance must be carefully tuned. As one recent analysis noted, analog/mixed-signal verification has the “highest causes of flaws” leading to chip re-spins ⁴. Unlike digital, where logic can often be simulated quickly, analog circuits often require SPICE-level circuit simulation, covering hundreds of corners and Monte Carlo runs. Running thousands of PVT (process, voltage, temperature) combinations in SPICE can extend simulation times into months under traditional licensing. Even a single analog block may take days or weeks to simulate to signoff accuracy.
The analog workflow also involves heavy manual effort. Designers often hand-tune transistor sizes and layout to meet specs, and custom verification scripts or co-simulation must be written. As a Semiengineering survey noted, “Analog design has remained a manual task performed by experts” and has not kept pace with automated digital flows ⁴. Layout and place-and-route for analog are also slow and custom-driven. This manual burden lengthens schedules and limits iteration: if a SPICE run takes days, a single analog debug cycle may set a team back weeks.
Key analog challenges include:
These challenges have grown as analog content per chip has increased. As analog blocks get embedded within mixed-signal SoCs, errors and slowdowns have multiplied. Overcoming them requires a new paradigm – one that brings automation, higher abstraction, and AI to analog design.
The old model of analog design – isolated blocks handed off at final stages – is quickly giving way to a system-level, digital-centric approach. Two key trends define this shift:
Despite these advances, a gap remains: analog cycles are still ~2–3X slower than digital on average. The industry needs digital-aware, AI-powered analog tools to close that gap. Tools must natively handle mixed digital/analog scenarios. AI and optimization technologies (ML-based circuit tuning, surrogate models) can reduce the brute-force simulation effort. In summary, analog design is evolving from component-level, manual artistry to automated, system-level engineering – but much work remains to fully close the gap with digital productivity ⁴.
To meet these trends and challenges, Synopsys has broadened its analog and mixed-signal EDA platform into an AI-driven, heterogeneous ecosystem. Key elements include:
Overall, Synopsys’ strategy is to marry analog expertise with digital-age tooling. By embedding AI/ML and high-performance compute into its AMS products, Synopsys enables analog teams to iterate designs faster, close loops sooner, and hit tight schedules.
Synopsys offers several unique technologies – not found in competing EDA suites – that tackle specific analog design hurdles:
By addressing specific analog pain points – mixed-signal co-sim, memory interface timing, custom-block timing, functional correctness – these technologies set Synopsys apart. Customers gain faster, more accurate verification at steps where errors once lurked undetected.
Synopsys Cloud amplifies these tools with unprecedented agility. Because the analog EDA suite runs in a cloud environment with pay-per-use licensing, startups and teams can ramp up in hours (literally days instead of weeks) without traditional setup headaches. The Frost & Sullivan report highlights how Cloud’s built-in license management and minute-by-minute billing “provides unlimited licenses to accommodate peak demands”. In practice, a team can spin up hundreds of PrimeSim SPICE instances for overnight regression runs, something that would be cost-prohibitive under fixed licensing.
This was exemplified in the TetraMem success story: the analog IMC accelerator team, distributed globally, used Synopsys Cloud to deploy a complete analog SoC flow within days ¹⁴. They had on-demand access to custom design tools and virtual desktop environments, eliminating lengthy CAD installations. The pay-per-use model let them grab extra licenses only during crunch times – a huge productivity boost. As TetraMem’s team puts it, the cloud solution provides a “seamless, unified mixed-signal SoC design environment” that gets startups into production in days, not weeks.¹⁴
Flexible Cloud licensing also means no more license shortage bottlenecks. Teams can dynamically scale EDA and compute resources up and down with the project stage. Synopsys cites Rubini Kamal (Frost analyst) saying “Cloud removes licensing constraints, enabling more efficient design workflows” ¹⁵. In the AI-driven era, where runs and iterations explode, Cloud’s elasticity is a game-changer for analog teams.
Synopsys is demonstrating clear leadership in tackling today’s analog design crisis. By winning Frost & Sullivan’s Analog In-Memory Compute innovation award ¹⁵, the company’s efforts in AI-augmented analog EDA have been formally recognized. Underlying this are solid customer outcomes: benchmark results from customers show multi-fold accelerations in simulation and characterization (often 10X or more).
Synopsys’ comprehensive response spans expanded tools, novel algorithms, and cloud delivery. AI-driven optimizers like ASO.ai give analog teams smart shortcuts, and GPU-SPICE cuts runtimes dramatically. Unique flows (RTVS, Hybrid Timing, NanoTime, ESP) address long-standing pain points in mixed-signal and memory designs. Combined with Synopsys Cloud’s on-demand scaling, customers can overcome the traditional analog bottlenecks.
In summary, Synopsys is enabling chip designers to meet the 21st-century demands of AI, 5G, and autonomous systems. Synopsys analog EDA portfolio – powered by AI and accelerated compute – is helping analog engineers iterate faster, semiconductor companies deliver on time, and investors capture the value of reduced risk and improved productivity. These innovations ensure Synopsys remains at the forefront of analog and mixed-signal chip design.
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