Synopsys Leads AI-Powered Analog Design Innovation

Sumit Vishwakarma

Jun 23, 2025 / 9 min read

Synopsys was recently recognized as the 2025 Technology Innovation Leader for Analog In-Memory Computing by Frost & Sullivan, underscoring its leadership in AI-powered analog and mixed-signal (AMS) EDA solutions. This recognition reflects Synopsys’ strategic focus, continuous innovation, and deep collaboration with customers to address the evolving demands of semiconductor design. As modern chip architectures become increasingly analog-aware—driven by the need for ultra-high-speed data movement in AI training, V2X communication in automotive, and high-performance RF in 5G and IoT—the role of analog design has become mission-critical. With analog content embedded in nearly every advanced system, the pressure to deliver accurate, efficient, and scalable AMS designs has never been higher. Synopsys delivers a modern, integrated AMS design platform that is purpose-built to meet these demands, setting the stage for the key challenges and breakthrough solutions that follow.

Award-Winning AI-Powered Analog and Mixed Signal EDA Solutions

Semiconductor Trends Driving Analog Design Demand

Modern chip designs are dominated by AI, connectivity, and automotive trends – all of which place new demands on analog front-ends and mixed-signal IP. AI training and inference require “tsunamis” of data to move between compute nodes 1 . Hyperscale data centers and AI accelerators depend on ultra-high-speed I/O to meet growing bandwidth demands. To support this, next-generation SerDes PHYs, capable of 100 Gbps per lane and beyond, are essential ². In fact, the bandwidth needs of generative AI and large language models are pushing SerDes standards from 56G/112G into 224G and beyond ². Each doubling of SerDes speed adds huge challenges in signal integrity and analog design.

Meanwhile, automotive and IoT growth is pushing analog integration. Connected and autonomous vehicles use multiple sensors (radar, LIDAR, cameras) and support V2X (vehicle-to-everything) communications over 5G/C-V2X. These systems require RF front-ends, high-speed ADCs/DACs, and custom PHYs, driving more analog/mixed-signal SoCs ³. In mobile and wireless markets, 5G/6G RF transceivers and Wi-Fi 6/7 components continue expanding, further swelling analog IP demand.

In short, virtually every modern application – from AI to automotive to wireless – needs sophisticated analog and AMS designs. This confluence of trends is creating an unprecedented surge in analog design complexity and volume, placing analog back at the center of innovation.

Challenges in Analog and Mixed-Signal Design

Analog design today is labor-intensive and fraught with difficulty. Analog circuits are highly sensitive to process variations, temperature and parasitics; each device’s performance must be carefully tuned. As one recent analysis noted, analog/mixed-signal verification has the “highest causes of flaws” leading to chip re-spins ⁴. Unlike digital, where logic can often be simulated quickly, analog circuits often require SPICE-level circuit simulation, covering hundreds of corners and Monte Carlo runs. Running thousands of PVT (process, voltage, temperature) combinations in SPICE can extend simulation times into months under traditional licensing. Even a single analog block may take days or weeks to simulate to signoff accuracy.

The analog workflow also involves heavy manual effort. Designers often hand-tune transistor sizes and layout to meet specs, and custom verification scripts or co-simulation must be written. As a Semiengineering survey noted, “Analog design has remained a manual task performed by experts” and has not kept pace with automated digital flows ⁴. Layout and place-and-route for analog are also slow and custom-driven. This manual burden lengthens schedules and limits iteration: if a SPICE run takes days, a single analog debug cycle may set a team back weeks.

Key analog challenges include:

  • Complexity & Variability: Each analog sub-block (ADC, PLL, SerDes frontend, etc.) has many design knobs. Covering all corner cases (voltage, temp, ageing) multiplies simulation needs. Performance targets (linearity, noise, gain, etc.) must be balanced manually.
  • Long Simulation Times: Gold-standard analog signoff needs extensive SPICE or fastSPICE. Without acceleration, millions of transistors can tie up CPU cores for days.
  • Manual Verification: Analog lacks a unified verification framework. Engineers often “throw an analog block over the wall” to backend, leading to late surprises. Integrating analog with digital testbenches is still evolving.

These challenges have grown as analog content per chip has increased. As analog blocks get embedded within mixed-signal SoCs, errors and slowdowns have multiplied. Overcoming them requires a new paradigm – one that brings automation, higher abstraction, and AI to analog design.

How Analog Design Is Changing

The old model of analog design – isolated blocks handed off at final stages – is quickly giving way to a system-level, digital-centric approach. Two key trends define this shift:

  • Digitalization of Analog: Many analog functions now incorporate digital or programmable elements. Examples include ADCs with digital calibration loops, digitally-assisted op-amps (using DSP to boost performance), on-chip DPLL/DFTs in RF, and fully-programmable analog IP. Analog components are increasingly verified within a digital framework. As one expert notes, modern analog blocks “such as ADCs with digital calibration loops or voltage regulators with digital trimming logic demand earlier, digital-aware verification” ⁴. In practice, designers are creating mixed-signal testbenches where analog blocks are run under digital stimulus, and co-simulation is used extensively. This blurs the line between analog and digital flows.
  • Modernization of Tools: Analog design is moving to advanced technology nodes (28nm and below) and more complex processes (FinFET, FD-SOI, etc.). Even emerging domains like photonics are coming into analog flows. Correspondingly, companies are shifting from old in-house scripts to commercial analog EDA. New tools now incorporate ML/AI and heterogeneous computing.

Despite these advances, a gap remains: analog cycles are still ~2–3X slower than digital on average. The industry needs digital-aware, AI-powered analog tools to close that gap. Tools must natively handle mixed digital/analog scenarios. AI and optimization technologies (ML-based circuit tuning, surrogate models) can reduce the brute-force simulation effort. In summary, analog design is evolving from component-level, manual artistry to automated, system-level engineering – but much work remains to fully close the gap with digital productivity ⁴.

Synopsys’ Strategic Response

To meet these trends and challenges, Synopsys has broadened its analog and mixed-signal EDA platform into an AI-driven, heterogeneous ecosystem. Key elements include:

  • AI-Powered Optimization (ASO.ai): Synopsys ASO.ai leverages machine learning to automate analog design tasks, from sizing and layout optimization to corner analysis. ASO.ai “unleashes the power of AI to analog design,” accelerating workflows that traditionally required expert tuning ⁵. For example, when migrating an analog IP to a new node, ASO.ai can explore thousands of sizing options automatically and suggest optimal parameters, cutting tuning time dramatically.
  • GPU-Accelerated Simulation: The PrimeSim simulator harnesses GPUs and multi-core CPUs to shrink SPICE runtimes. Now circuit designers can efficiently handle large post-layout circuits, previously unsolvable, with SPICE-level accuracy, delivering faster runtimes and sign-off precision ⁶. In practice, a GPU-accelerated SPICE can turn a multi-day analog sim into just a few hours, enabling designers to run far more iterations. (One reported use shows memory timing analysis going from 19 days to 4 days – a 5X speedup – by enabling PrimeSim on GPUs.) ⁷.
  • Unified, Open Platform: Synopsys promotes a modern, open chip-design platform. All leading foundry PDKs (TSMC, GlobalFoundries, Samsung, etc.) are fully supported down to 28 nm and below, ensuring designers can use PrimeSim, Custom Compiler, and related tools natively with advanced processes. The platform supports hybrid analog/digital flows (through tool interoperability) and is extensible via APIs. This openness lets customers integrate Synopsys analog tools alongside their digital flows for a seamless SoC design experience.
  • Productivity Gains: The combination of new tools yields dramatic productivity boosts. In customer case studies, teams report that analog circuit verification “reduced run times from days or weeks down to hours or days” ⁸. Another user cited a 12X overall runtime gain after migrating to the new flow ⁸. Synopsys often cites “2–5X faster verification closure” and “5–10X productivity improvements” on analog-intensive projects – while achieving sign-off accuracy. For example, M31 (a leading IP provider) saw its IC characterization time cut by 15X and achieved 77% higher first-pass device yield using Synopsys Cloud and PrimeLib ⁹.

Overall, Synopsys’ strategy is to marry analog expertise with digital-age tooling. By embedding AI/ML and high-performance compute into its AMS products, Synopsys enables analog teams to iterate designs faster, close loops sooner, and hit tight schedules.

Differentiating Technologies Exclusive to Synopsys

Synopsys offers several unique technologies – not found in competing EDA suites – that tackle specific analog design hurdles:

  • Real-Time View Swapping (RTVS): Mixed-signal simulations often involve large digital testbenches with small analog blocks. RTVS enables the simulator to dynamically switch between an abstract digital model and a detailed analog model “on the fly.” During co-simulation, critical analog blocks are simulated in full SPICE view when needed and otherwise replaced by faster digital logic models. This reduces sim time while preserving accuracy for key periods. As one Synopsys blog notes, RTVS “allows dynamic switching between digital and analog abstractions for critical blocksto help accelerate [mixed-signal] verification” ¹⁰.  Incorporating such digital design and verification techniques into mixed signal development flows can shift the process left for faster turnaround time.
  • PrimeSim Hybrid Timing (for High-BW Memories): Memory IP like HBM/DDR and flash include custom analog circuits (I/O drivers, sense amps, etc.) and require detailed timing with on-chip power and IR drop. PrimeSim Hybrid Timing is an innovative flow that combines SPICE and fast timing analysis. The technology was demonstrated in a NAND Flash context: designers achieved “custom circuit simulation at digital speed,” alleviating SPICE bottlenecks ¹¹. Essentially, analog paths are simulated at transistor level where needed, while large portions of the design use fast static timing. The result is orders-of-magnitude faster signoff timing for memory interfaces – critically important for large HBM stacks.
  • Synopsys NanoTime (Transistor-Level STA): Traditional STA tools work on synthesized gates, not analog transistors. NanoTime fills this gap by performing foundry-certified transistor-level timing and signal integrity analysis. It exhaustively analyzes all internal timing paths and noise interactions within full-custom and IP blocks ¹². For example, NanoTime can verify a complex analog datapath or an embedded SRAM timing without requiring RTL. NanoTime then generates timing models that feed into PrimeTime, giving designers a golden reference for timing signoff. This is crucial for analog-rich SoCs: NanoTime can catch issues like substrate coupling or IR induced delays that would escape gate-level STA.
  • Synopsys ESP (Equivalence Checking): ESP is a formal verification tool tailored for custom analog/memory IP. It compares a transistor-level SPICE netlist against a behavioral or RTL model (e.g. Verilog) to prove they match. In a memory design, for instance, ESP can verify that redundancy logic and peripheral circuitry exactly implement the specification. As the Synopsys memory conference notes, ESP can “quickly verify that the redundancy logic added to the memory array is performing correctly” ¹³. In effect, ESP replaces thousands of manual tests by exhaustive formal checks, boosting confidence and coverage in standard cells, I/O, and memory IP blocks.

By addressing specific analog pain points – mixed-signal co-sim, memory interface timing, custom-block timing, functional correctness – these technologies set Synopsys apart. Customers gain faster, more accurate verification at steps where errors once lurked undetected.

Synopsys Cloud Advantage

Synopsys Cloud amplifies these tools with unprecedented agility. Because the analog EDA suite runs in a cloud environment with pay-per-use licensing, startups and teams can ramp up in hours (literally days instead of weeks) without traditional setup headaches. The Frost & Sullivan report highlights how Cloud’s built-in license management and minute-by-minute billing “provides unlimited licenses to accommodate peak demands”. In practice, a team can spin up hundreds of PrimeSim SPICE instances for overnight regression runs, something that would be cost-prohibitive under fixed licensing.

This was exemplified in the TetraMem success story: the analog IMC accelerator team, distributed globally, used Synopsys Cloud to deploy a complete analog SoC flow within days ¹⁴. They had on-demand access to custom design tools and virtual desktop environments, eliminating lengthy CAD installations. The pay-per-use model let them grab extra licenses only during crunch times – a huge productivity boost. As TetraMem’s team puts it, the cloud solution provides a “seamless, unified mixed-signal SoC design environment” that gets startups into production in days, not weeks.¹⁴

Flexible Cloud licensing also means no more license shortage bottlenecks. Teams can dynamically scale EDA and compute resources up and down with the project stage. Synopsys cites Rubini Kamal (Frost analyst) saying “Cloud removes licensing constraints, enabling more efficient design workflows” ¹⁵. In the AI-driven era, where runs and iterations explode, Cloud’s elasticity is a game-changer for analog teams.

Conclusion

Synopsys is demonstrating clear leadership in tackling today’s analog design crisis. By winning Frost & Sullivan’s Analog In-Memory Compute innovation award ¹⁵, the company’s efforts in AI-augmented analog EDA have been formally recognized. Underlying this are solid customer outcomes: benchmark results from customers show multi-fold accelerations in simulation and characterization (often 10X or more).

Synopsys’ comprehensive response spans expanded tools, novel algorithms, and cloud delivery. AI-driven optimizers like ASO.ai give analog teams smart shortcuts, and GPU-SPICE cuts runtimes dramatically. Unique flows (RTVS, Hybrid Timing, NanoTime, ESP) address long-standing pain points in mixed-signal and memory designs. Combined with Synopsys Cloud’s on-demand scaling, customers can overcome the traditional analog bottlenecks.

In summary, Synopsys is enabling chip designers to meet the 21st-century demands of AI, 5G, and autonomous systems.  Synopsys analog EDA portfolio – powered by AI and accelerated compute – is helping analog engineers iterate faster, semiconductor companies deliver on time, and investors capture the value of reduced risk and improved productivity. These innovations ensure Synopsys remains at the forefront of analog and mixed-signal chip design.


References:

  1. https://semiwiki.com/artificial-intelligence/353781-dvcon-2025-ai-and-the-future-of-verification-take-center-stage/ 
  2. https://semiengineering.com/224g-serdes-trend-and-solution/ 
  3. https://www.eetimes.com/weighing-design-challenges-for-wireless-socs-in-v2x/ 
  4. https://semiengineering.com/analog-creates-ripples-in-digital-verification 
  5. https://www.synopsys.com/ai/ai-powered-eda/aso-ai.html 
  6. https://www.synopsys.com/implementation-and-signoff/ams-simulation/primesim-spice.html 
  7. https://www.synopsys.com/events/memory-users-conference.html (Session: Accelerating Circuit Simulation using GPU, Veerbhadra Rao Boda, Engineering Manager, NVIDIA)
  8. https://www.synopsys.com/implementation-and-signoff/ams-simulation/snug-gets-wisdom.html 
  9. https://www.synopsys.com/success-stories/m31-faster-characterization-synopsys-cloud-primelib.html
  10. https://www.synopsys.com/blogs/chip-design/tools-accelerate-memory-chip-design.html 
  11. https://www.synopsys.com/events/memory-users-conference.html (Session: Custom Circuit simulation at Digital speed! Accelerating Fast SPICE Simulation in Flash Memory using PrimeSim Hybrid Timing, Yusuke Ono, Design Technology Specialist, Kioxia)
  12. https://www.synopsys.com/implementation-and-signoff/signoff/nanotime.html 
  13. https://www.synopsys.com/events/memory-users-conference.html (Session: High Verification Coverage with ESP in Full custom SRAM Memory Design, Anukriti Singh, SRAM Memory Circuit Designer, STMicroelectronics)
  14. https://www.synopsys.com/cloud/tetramem-success.html 
  15. https://www.frost.com/wp-content/uploads/2025/05/Synopsys-Award-Write-Up.pdf