Synopsys Interface IP Subsystems

Whether you need a single controller and PHY integration, a combination of multiple protocols, or complete subsystems with processors and the software stack, Synopsys experts deliver IP subsystems tuned to your SoC.

As both hardware and software complexity increases, you need more advanced and integrated IP solutions to meet your aggressive project schedules without compromising quality. Synopsys' configurable, pre-verified IP Subsystems deliver complete, complex functions that are ready to integrate into your SoC as-is, or be customized by your team or ours. 

By integrating specific IP blocks together in a single subsystem, Synopsys is providing you with another option to reduce your design and integration effort, lower design risk and accelerate time-to-market.

• Accelerate interface IP subsystem development for complex protocols, such as DDR, PCIe, USB, and Ethernet, as well as multiprotocol subsystems.
  
• Meet critical project schedules by using Synopsys IP protocol and SoC design experts to configure and customize the pre-designed subsystem to the unique SoC requirements.
• Minimize the subsystem integration effort through the use of pre-validated subsystem and verification tests focused on SoC integration
• Reduce overall development costs while enabling designers to focus on their key competencies.
• Provide functionality and value over simple integration of a PHY and controller by including a common register interface between the PHY and controller, debug logic, and more.
• Deliverables
  • Pre-configured, pre-validated Synopsys IP for controllers, PHYs and verification IP (VIP)
  • Supplemental subsystem logic for clock, reset, DMA, interrupts, and memory maps
  • Power management, debug, and testability logic
  • Complete subsystem verification environment that can also be leveraged for SoC verification:
    • Scoreboard, checkers and monitors for easy SoC debug
    • Comprehensive suite of tests that can be reused at SoC level