Achieving the Best Arm PPA: A Discussion with Sudhakar Jilla

Q: Please tell us how is the Arm-Synopsys relationship progressing?

Sudhakar Jilla:

Synopsys and Arm have collaborated for many decades to deliver optimized flows for the implementation of Arm cores. This collaboration has resulted in 100s of production Arm implementations designed using Synopsys software at different semiconductor companies. We have multiple teams working with Arm collaborating on new cores, new node support, library, and POP development. Recently, with the release of the Fusion Design Platform™ and Fusion Compiler™, we have placed an even higher emphasis on early collaboration with Arm for enablement of the next-generation mobile and infrastructure cores to enable our customers to achieve the best power, performance, and area (PPA). Arm Solutions Group (ASG) that I now lead is a centralized organization created to rapidly align and accelerate our execution in a holistic fashion. 

Q: What does the collaboration between Arm and Synopsys enable?

Sudhakar Jilla:

Arm and Synopsys collaborate across the design spectrum including design implementation, Silicon IP, high-performance verification, hybrid emulation, virtual prototypes, hybrid prototypes, and FPGA prototypes. ASG specifically focuses on Synopsys design implementation and signoff tools to develop and deliver core-specific QuickStart Implementation Kits (QiKs) that deliver the recipes and methodologies to achieve the best PPA. Our customers can get access to these QiKs from Arm or Synopsys. The benefits of this collaboration are evident in the growing number of customer tapeouts of Arm processor cores using Synopsys tools. Many of these successes are public, for instance, we recently announced tapeouts at a large leading-edge customer that has Cortex®-A78, Cortex-X1, and Mali-G78 cores in their SoC. 

Q: What technologies have been developed for Arm core hardening?

Sudhakar Jilla:

Synopsys is constantly evolving and innovating to deliver a comprehensive solution to customers; these include new tools, tool enhancements, and comprehensive methodologies. Fusion Compiler embodies this relentless commitment to innovation and our ambition to enable design teams to push the envelope and drive increased agility and differentiation. Founded on a single data-model and incorporating common interleaved optimization engines built around industry-golden signoff engines, Fusion Compiler delivers optimal levels of PPA in the most convergent manner with the fastest and most predictable time-to-results. Integration with PrimeTime®, StarRC™, PrimePower, and Ansys RedHawk technologies enables unique signoff accuracy during implementation, significantly reducing margins and pessimism in the design flow, and driving better optimization transforms for unmatched results.

Q: Specific to power, how is Synopsys addressing this in Arm core design?

Sudhakar Jilla:

Achieving a low power footprint is key to many of the designs with Arm cores. Fusion Compiler enables total-power optimization throughout the flow with a common costing of the power transforms. These power optimization technologies include hierarchical clock gating, power-driven structuring and restructuring, XOR self-gating, and power-driven mapping. Other technologies that also come to mind are activity-driven placement, power-aware CTS, and power-aware CCD. Fusion Compiler includes the ability to automatically handle complex multi-voltage design styles including dynamic voltage frequency scaling (DVFS) with support for power management cells such as level shifters, isolation cells, and MTCMOS power switches as captured in the Unified Power Format (UPF).

Q: What are some of the biggest challenges that you see customers facing in their design process?

Sudhakar Jilla:

One does not need to look into a crystal ball to see that the cores of the future will be larger, run faster, push power/energy envelopes, and continue to require ever-shrinking design cycles. Orthogonally, the foundries also continue to innovate with new gate-all-around FETs at 3nm and 2nm. These innovations in new transistors structures will require a significant change in tool technologies and methodologies to achieve the best PPA. 

Q: How are some innovations that will help designers address these challenges?

Sudhakar Jilla:

Our collaboration with Arm has been responsible for the development and deployment of numerous innovative technologies to address critical design challenges. Most recently, we are collaborating on RTL Architect, a fast, multi-dimensional predictive tool that enables RTL designers to predict power, performance, area, and congestion impact of their RTL changes. Arm RTL designers can now pinpoint inefficiencies in their HDL source code and improve its quality. We are also taking advantage of the ANSYS and Synopsys partnership where we are taking advantage of ANSYS’s best in class power integrity and reliability offerings to create an integrated flow with Fusion Compiler for robust design optimization by eliminating late-stage surprises in Arm core implementation. And of course, we continue to build in AI/ML into the platform that learns continuously to improve customer environments and boosts designer productivity by speeding up analyses, predicting results that drive better decision-making, and leveraging past learning to intelligently guide debug.

Q: Where can one find information and download the QuickStart Implementation Kits? Where should I go to if I need ASG’s help?

Sudhakar Jilla:

That’s easy, go to here. We are constantly rolling out new QIKs so check with Arm or Synopsys often to get access to the latest version. You can reach out to your account Sales and/or AE team to connect with ASG.

Q: Thanks for your time, Sudhakar. Is there anything else you would like to add?

Sudhakar Jilla:

Thank you for this opportunity today. We are very excited about our strong partnership with Arm.  We recently inked a new multi-year strategic agreement to deliver full-flow solutions that help accelerate the design and verification of Arm-based SoCs. We look forward to continuing our close partnership with Arm and enabling our mutual customers to deliver the best-in-class Arm implementation and SoCs that will drive the digital revolution of tomorrow.