Synopsys Webinar | Available On Demand

RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues.


Synopsys Formality ECO offers an efficient and accurate solution for RTL ECO by automating the comprehensive ECO flow, analysing differences between original RTL and ECO RTL, generating patches, and validating changes. Formality ECO also supports aggressive RTL optimization techniques, including retiming and auto ungrouping, while providing advanced analysis and debug features to streamline the ECO process.


In this Synopsys webinar, presenters from SiFive will share the advantages of Synopsys Formality ECO on their overall ECO cycle which has enhanced patching capabilities and resulted in faster verification runtime leading to improved TAT. With the retimed and flattened design, it is difficult to generate the sizable patch for fast CPUs designs targeted by SiFive. SiFive designs have strict requirements on the patch size, patch affecting hierarchies, changes applicable to RTL and ease of implementation at route_opt stage. By using Synopsys Formality ECO suite, SiFive has been able to generate a hassle-free patch and verify it 3-5x faster than traditional formal verification ensuring performance of the CPU.  


Listed below are the industry leaders scheduled to speak.

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Vivek Upadhyaya

Technical Director

Vivek Upadhyaya brings over 20 years of extensive experience in VLSI industry, specializing in High-Speed CPU Implementation. Currently he is holding esteemed position as a Technical Director at SiFive in Physical Implementation Group. His previous roles encompassed notable companies such as Broadcom, Cadence, Intel, and STMicroelectronics, focusing on RTL-to-GDSII implementation. He is graduate from CCS University Meerut, UP. 

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Rupali Kale Gaikwad

Staff Engineer

Rupali Kale Gaikwad is a Staff Engineer at Synopsys, holds Master’s degree in Microelectronics from BITS, Pilani. Over a span of 12 years, she has worked on various advanced node ASIC designs of different sectors including automotive, networking, modem, healthcare, high speed CPU implementation. In Synopsys she is responsible for Ecosystem customer success for complete RTL2GDS solution.

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